MPC5200B(2006) データシートの表示（PDF） - Freescale Semiconductor

部品番号

コンポーネント説明

メーカー

MPC5200B
(Rev.:2006)

SDRAM/DDR Memory Controller

Freescale Semiconductor 

Electrical and Thermal Characteristics

3.3.5 SDRAM

3.3.5.1 Memory Interface Timing-Standard SDRAM Read Command

Table 18. Standard SDRAM Memory Read Timing

Sym

Description

Min

tmem_clk MEM_CLK period

tvalid Control Signals, Address and MBA Valid after

rising edge of MEM_CLK

thold Control Signals, Address and MBA Hold after

rising edge of MEM_CLK

DMvalid DQM valid after rising edge of MEM_CLK

DMhold DQM hold after rising edge of MEM_CLK

datasetup MDQ setup to rising edge of MEM_CLK

datahold MDQ hold after rising edge of MEM_CLK

7.5

—

tmem_clk*0.5

—

tmem_clk*0.25-0.7

—

0.2

Max

—

tmem_clk*0.5+0.4

—

tmem_clk*0.25+0.4

—

0.3

—

Units SpecID

ns

A5.1

ns

A5.2

ns

A5.3

ns

A5.4

ns

A5.5

ns

A5.6

ns

A5.7

MEM_CLK

Control Signals

DQM (Data Mask)

MDQ (Data)

MA (Address)

MBA (Bank Selects)

tvalid

thold

Active

NOP

DMvalid

READ NOP

DMhold

NOP NOP NOP

NOP

datasetup

tvalid

Row

tvalid

thold

thold

Column

datahold

NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN

Figure 5. Timing Diagram—Standard SDRAM Memory Read Timing

3.3.5.2 Memory Interface Timing-Standard SDRAM Write Command

In Standard SDRAM, all signals are activated on the MEM_CLK from the Memory Controller and

captured on the MEM_CLK clock at the memory device.

MPC5200B Data Sheet, Rev. 1

20

Freescale Semiconductor

Share Link: