CS5540 データシートの表示（PDF） - Cirrus Logic

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CS5540

Low-Power, Low-Voltage, 24 - Bit ∆Σ ADC

Cirrus Logic 

CS5540

LIST OF FIGURES

Figure 1. Continuous Running SCLK Timing (Not to Scale) ........................................................... 9

Figure 2. SDO Read Timing (Not to Scale)..................................................................................... 9

Figure 3. Multiplexer Configuration. .............................................................................................. 10

Figure 4. Input model for AIN+ and AIN- pins. .............................................................................. 10

Figure 5. Resolution vs. Voltage Reference.................................................................................. 11

Figure 6. Input model for VREF+ and VREF- pins........................................................................ 11

Figure 7. CS5540 Configured with a single +3.0 V Supply. .......................................................... 12

Figure 8. Command and Data Word Timing. ................................................................................ 13

Figure 9. Self Calibration of Offset. ............................................................................................... 13

Figure 10. Self Calibration of Gain. ............................................................................................... 14

Figure 11. Digital Filter Response................................................................................................. 15

LIST OF TABLES

Table 1. Output Conversion Data Register Description (24 bits + flags) ...................................... 15

Table 2. CS5540 24-Bit Bipolar Output Coding ............................................................................ 15

DS503PP1

3

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