HY27UV08BG5M データシートの表示（PDF） - Hynix Semiconductor

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HY27UV08BG5M

32Gb NAND FLASH

Hynix Semiconductor 

1

Preliminary

HY27UV08BG(5/D/F)M Series

32Gbit (4Gx8bit) NAND Flash

2. BUS OPERATION

There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,

Data Output, Write Protect, and Standby.

Typically glitches less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not

affect bus operations.

2.1 Command Input.

Command Input bus operation is used to give a command to the memory device. Commands are accepted with Chip

Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising

edge of Write Enable. Moreover for commands that start a modify operation (write/erase) the Write Protect pin must

be high. See figure 5 and table 12 for details of the timings requirements. Command codes are always applied on

IO7:0, disregarding the bus configuration (X8/X16).

2.2 Address Input.

Address Input bus operation allows the insertion of the memory address. To insert the 31 addresses is needed to

access the 32Gbit, 5 clock cycles are needed. Addresses are accepted with Chip Enable low, Address Latch Enable

High, Command Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for

commands that start a modify operation (write/erase) the Write Protect pin must be high. See figure 6 and table 12 for

details of the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration (X8).

2.3 Data Input.

Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and

timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command

Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figure

7 and table 12 for details of the timings requirements.

2.4 Data Output.

Data Output bus operation allows to read data from the memory array and to check the status register content, the ID

data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write Enable High, Address

Latch Enable low, and Command Latch Enable low. See figures 8,9,10,11,12 and table 12 for details of the timings

requirements.

2.5 Write Protect.

Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not

start and the content of the memory is not altered or it is interrupted without guarantee about memory content not

being altered. Write Protect pin is not latched by Write Enable, so to ensure protection even during power up phases.

2.6 Standby.

In Standby the device is deselected, outputs are disabled and Power Consumption reduced. Stand-by is obtained hold-

ing high, at least for 10 us, CE pin.

Rev 0.0 / Sep. 2006

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