T7237A データシートの表示（PDF） - Agere -> LSI Corporation

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T7237A

Compliance with the New ETSI PSD Requirement

Agere -> LSI Corporation 

T7256 Single-Chip NT1 (SCNT1) Transceiver

Data Sheet

January 1998

Table of Contents (continued)

Tables

Page

Table 1. Pin Descriptions ...........................................................................................................................................6

Table 2. U-Interface Bit Assignment ........................................................................................................................13

Table 3. Line Transmission Code .............................................................................................................................18

Table 4. Global Device Control—Device Configuration (Address 00h) ....................................................................20

Table 5. Global Device Control—U-Interface (Address 01h) ...................................................................................22

Table 6. Global Device Control—S/T-Interface (Address 02h) .................................................................................23

Table 7. Data Flow Control—U and S/T B Channels (Address 03h)........................................................................25

Table 8. Data Flow Control—D Channels and TDM Bus (Address 04h)..................................................................26

Table 9. TDM Bus Timing Control (Address 05h)..................................................................................................... 27

Table 10. Control Flow State Machine Control—Maintenance/Reserved Bits (Address 06h) .................................28

Table 11. Control Flow State Machine Status (Address 07h) ..................................................................................29

Table 12. Control Flow State Machine Status—Reserved Bits (Address 08h) ........................................................30

Table 13. eoc State Machine Control—Address (Address 09h) ..............................................................................31

Table 14. eoc State Machine Control—Information (Address 0Ah) .........................................................................32

Table 15. eoc State Machine Status—Address (Address 0Bh) ...............................................................................32

Table 16. eoc State Machine Status—Information (Address 0Ch) ..........................................................................32

Table 17. Q-Channel Bits (Address 0Dh).................................................................................................................33

Table 18. S Subchannels 1—5 (Address 0Eh—12h)...............................................................................................33

Table 19. U-Interface Interrupt Register (Address 13h) ...........................................................................................34

Table 20. U-Interface Interrupt Mask Register (Address 14h)..................................................................................35

Table 21. S/T-Interface Interrupt Register (Address 15h).........................................................................................36

Table 22. S/T-Interface Interrupt Mask Register (Address 16h) ...............................................................................36

Table 23. Maintenance Interrupt Register (Address 17h) ........................................................................................37

Table 24. Maintenance Interrupt Mask Register (Address 18h)...............................................................................37

Table 25. Global Interrupt Register (Address 19h) ..................................................................................................38

Table 26. Stand-Alone Mode ...................................................................................................................................45

Table 27. Microprocessor Mode...............................................................................................................................45

Table 28. STLED States ..........................................................................................................................................46

Table 29. T7256 Reference Schematic Parts List ....................................................................................................56

Table 30. Line-Side Resistor Requirements ............................................................................................................58

Table 31. Motorola MC68302 SCC Options.............................................................................................................62

Table 32. PCM Channel Selection ...........................................................................................................................63

Table 33. SPEC_V2 Functions ................................................................................................................................69

Table 34. SPEC_V2 Interface Connector Pinouts....................................................................................................71

Table 35. Power Consumption .................................................................................................................................74

Table 36. Digital dc Characteristics (Over Operating Ranges) ................................................................................74

Table 37. S/T-Interface Receiver Common-Mode Rejection ....................................................................................75

Table 38. Fundamental Mode Crystal Characteristics .............................................................................................75

Table 39. Internal PLL Characteristics .....................................................................................................................75

Table 40. TDM Bus Timing ....................................................................................................................................... 76

Table 41. Clock Timing.............................................................................................................................................77

Table 42. RESET Timing..........................................................................................................................................77

Table 43. Power Dissipation Variation ....................................................................................................................101

Table 44. Power Dissipation of CKOUT .................................................................................................................101

Table 45. Power Consumption ...............................................................................................................................102

4

Lucent Technologies Inc.

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