MX802 データシートの表示（PDF） - CML Microsystems Plc
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MX802 Datasheet PDF : 24 Pages
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DVSR CODEC
4
2 Signal List
MX802
J/LH8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LH
Signal
Description
RAS2
Row Address Strobe 2 This pin should be connected to the Row
Address Strobe input of the second 1Mbit DRAM chip (if used).
1 RAS1
2 Write Enable
Row Address Strobe 1 This pin should be connected to the Row
Address Strobe input of the first DRAM chip.
( WE ) The DRAM of Read/Write control pin.
Xtal
This is the output of the 4.0MHz on –chip clock oscillator. External
components are required at the output when a Xtal is used. A Xtal
cannot be used with the 24-pin version.
3 Xtal/Clock
This is the input to the on-chip clock oscillator inverter. A 4.0MHz Xtal
or externally derived clock should be connected here. See Figure 2.
This clock provides timing for on-chip elements, filters, etc. A Xtal
cannot be used with the 24-pin version. Various Xtal frequencies can
be used with this device. See Table 5 for Sampling Rate Variations.
4 IRQ
Interrupt Request The output of this pin indicates an interrupt condition
to the microcontroller by going to logic’0’. This ‘wire-or able’ output,
enabling the connection of up to 8 peripherals to 1 interrupt port on the
microcontroller. This pin is an open drain output. It therefore has a low
impedance pulldown to logic ‘0’ when active and a high impedance
when inactive. Conditions indicated by this function are Power Reading
Ready, Play Command Complete, and Store Command Complete.
5 Serial Clock
This is the C-BUS serial clock input. This clock, produced by the
microcontroller, is used to transfer timing commands and data to and
from the DVSR Codec. See timing diagrams. Clock requirements vary
for different MX802 functions.
6 Command Data This is the C-BUS serial data input from the microcontroller. Data is
loaded to this device in 8-bit bytes, MSB (bit 7) first, and LSB (bit 0) last,
synchronized to the Serial clock. See Timing diagrams.
7 CS
Chip Select : The C-BUS data transfer control function, this input is
provided by the microcontroller. Command Data transfer sequences are
initiated, completed, or aborted by the CS signal. See Timing
Diagrams.
8 Reply Data
9 VBIAS
10 Audio Out
11 Audio In
12 VSS
13 Encoder Out
(ENO)
This is the C-BUS serial data output to the microcontroller. The
transmission of Reply Data bytes is synchronized to the Serial Data
Clock under the control of the Chip Select input. This 3-state output s
held at high impedance when not sending data to the microcontroller.
See Timing diagrams.
This is the output of the on-chip analog circuitry bias system, held
internally at VDD/2. This pin should be decoupled to VSS by capacitor
C1. See Figure 2.
This is the Analog signal out.
This is the audio (speech) input. The signal to this pin must be AC
coupled by capacitor C4 and decoupled to VSS by HF capacitor C6. For
optimum noise performance this input should be driven from a source
impedance of less than 100.
Negative Supply (GND)
DRAM Data In/A0/Direct Access -- This is connected to the DRAM data
input and address line A0. With no DRAM used, this output is available
in a Direct Access mode as the Delta Encoder digital data Output.
Direct Access control is achieved by Control Register byte 1, bit 7.
1998 MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480033.008
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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