FireLink 1394 OHCI
82C881
5.3 PCI Configuration Registers
The PCI Configuration space registers implemented in the 82C881 are listed in the following table. They are not affected by
bus reset/soft reset.
The configuration space of the PCI 1394 OHCI controller is accessed through Mechanism #1 as Device #X (Device # depends
on which AD line is connected to the IDSEL input), Function #0, hereafter referred to as PCICFG.
5.3.1 PCI Configuration Space (PCICFG 00h to 3Fh)
7
6
5
4
3
2
PCICFG 00h
PCICFG 01h
Vendor Identification Register (RO)
1
0
Default = 45h
Default = 10h
PCICFG 02h
PCICFG 03h
Device Identification Register (RO)
Default = 81h
Default = C8h
PCICFG 04h
Command Register - Byte 0
Wait cycle
control:
Core does not
need to insert a
wait state
between
address and
data on the AD
lines. This bit is
always 0.
PERR#
(response)
detection
enable bit:
0 = PERR# not
asserted
1 = Core
asserts
PERR#
when
receiving
data agent
and data
parity error
detected.
VGA palette
snooping:
This bit is
always 0.
Postable
memory write
command:
Not used when
core is a
master. This bit
is always 0.
Special Cycles:
Core does not
run Special
Cycles on PCI.
This bit is
always 0.
Core can run
PCI master
cycles:
0 = Disable
1 = Enable
PCICFG 05h
Command Register – Byte 1
Reserved: These bits are always 0.
Default = 00h
Core responds
as a target to
memory
cycles.
Core responds
as
a target to I/O
cycles:
0 = Disable
1 = Enable
0 = Disable
1 = Enable
Default = 00h
Back-to-back
SERR#
enable:
(response)
Core only acts
as a master to a
detection
enable bit:
single device, 0 = SERR# not
so this
asserted
functionality is
not needed.
This bit is
always 0.
1 = Core can
assert
SERR#
PCICFG 06h
Fast back-to- Reserved: These bits are always
back capability: 0.
Core does not
supports fast
back-to-back
transactions
when
transactions are
not to same
agent. This bit
is always 0.
Status Register – Byte 0
PCI Power
Reserved: These bits are always 0.
Management
Capability (RO)
1 = Yes
(always)
Default = 80h
912-2000-031
Revision: 1.0
®
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