SBPH400-3 データシートの表示（PDF） - STMicroelectronics
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SBPH400-3 Datasheet PDF : 43 Pages
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SBPH400-3
port state. If all ports are in a low power state, and the PHY/Link interface is disabled, then the
SBPH400 implements the necessary delays to allow the SBPH400 core to enter a low power
state in future versions with no functional or timing change.
2.5 Data encoder/decoder
The data encoder/decoder implements the SGS-Thomson patented “Data/Strobe” clock
encoding technique, as described in the 1394 specification. Data to be transmitted is serialized
and encoded into the appropriate Data and Strobe signals. These are send simultaneously to
all active ports for outputting. All output is clocked by the SBPH400 clock derived from the local
crystal. Note that data to be transmitted may be received from an incoming port, or from the
link interface.
Data received from a port (only at most one port can be receiving data at any one time) is
resynchronized to the local clock using a small elastic buffer, as the clock frequency of the
incoming data may differ (by up to 200 ppm) from the local clock. The buffer is sized to avoid
underflow or overflow for the longest possible packet.The data is repeated to the ports and to
the link layer as described above, using the local reference clock.
2.6 Bus reset, arbitration and control
The SBPH400 enters bus reset on power reset, if the reset signal is sensed on any connected
port’s arbitration signal lines, on a request from a link layer device, on resume from suspend
or on connection of detection on any port (possibly after a delay, to allow for an incoming
reset), on loss of TpBias on an active parent port, on entry to suspend as a result of the peer
port being suspended or disabled, or if the device stays in any state other than Idle, Tree-ID
start, Transmit or Receive for longer than 300 µsec. In some circumstances, the device will
arbitrate for the bus before generating a reset signal, as defined in the P1394a proposal. This
results in minimum disruption to high priority traffic.
On entry to reset, the arbitration control logic enters a Tree-ID phase. Either the node will be
identified an isolated node, or the node will be identified as the root, and all active ports will be
identified as child ports, or one active port will be the port to the node’s parent, and the other
active ports will be identified as child ports.
The control logic will then engage in Self-ID, in which all nodes are allocated a node-ID and
exchange self-ID packets (see 2.7.2). All received self-ID packets are passed to the link layer
device. Speed capabilities are exchanged during the Self-ID process with all connected active
nodes.
In normal operation, the control logic implements the functions of the root, should the result of
the Tree-ID process be that this node becomes the root.
The control logic accepts arbitration requests from either the local link or any port. Upon receipt
of an arbitration request, the request is accepted locally (if the node is the root) or repeated
towards the root node via the parent port. Data Prefix (01) is transmitted on all other ports,
which indicates that any arbitration request from these ports is rejected.
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