LP62S2048A-T データシートの表示（PDF） - AMIC Technology
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LP62S2048A-T Datasheet PDF : 18 Pages
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LP62S2048A-T Series
256K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
General Description
Power supply range: 2.7V to 3.6V
Access times: 55/70 ns (max.)
Current:
Very low power version: Operating: 55ns: 25mA (max.)
70ns: 20mA (max.)
Standby: 10µA (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Output enable and two chip enable inputs for easy
application
Data retention voltage: 2V (min.)
Available in 32-pin SOP, TSOP, TSSOP (8X13.4mm
forward & reverse type) and 36-pin CSP packages
The LP62S2048A-T is a low operating current 2,097,152-bit
static random access memory organized as 262,144 words by
8 bits and operates on a low power supply range: 2.7V to 3.6V.
It is built using AMIC's high performance CMOS process.
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN and
device enable and an output enable input is included for easy
interfacing.
Data retention is guaranteed at a power supply voltage as low
as 2V.
Product Family
Product Family
LP62S2048A
Operating
Temperature
-25°C ~ +85°C
VCC
Range
2.7V~3.6V
Speed
55ns / 70ns
Power Dissipation
Data Retention
(ICCDR, Typ.)
Standby
(ISB1, Typ.)
Operating
(ICC2,
Typ.)
0.5µA
0.5µA
3mA
Package Type
32L SOP
32L TSOP
32L TSSOP
(Forward type)
32L TSSOP
(Reverse type)
36L CSP
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
(August, 2004, Version 1.2)
1
AMIC Technology, Corp.
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