IDT7027L25G データシートの表示（PDF） - Integrated Device Technology

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IDT7027L25G

HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7027S/L

High-Speed 32K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side(1)

tSAA

tOH

A0-A2

SEM

I/O0

R/W

VALID ADDRESS

tAW

tWR

tEW

tDW

DATAIN

VALID

tAS

tWP

tDH

VALID ADDRESS

tACE

tSOP

DATAOUT

VALID(2)

tSWRD

tAOE

OE

Write Cycle

Read Cycle

NOTES:

1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle), refer to Chip Enable Truth Table.

2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.

3199 drw 09

Timing Waveform of Semaphore Write Contention(1,3,4)

A0"A"-A2"A"

MATCH

SIDE(2) "A"

R/W"A"

SEM"A"

A0"B"-A2"B"

(2)

SIDE "B"

R/W"B"

tSPS

MATCH

SEM"B"

3199 drw 10

NOTES:

1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH (refer to Chip Enable Truth Table).

2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.

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