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IDT7027S(2018) データシートの表示(PDF) - Integrated Device Technology

部品番号
コンポーネント説明
一致するリスト
IDT7027S
(Rev.:2018)
IDT
Integrated Device Technology IDT
IDT7027S Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Waveform of Read Cycles(5)
ADDR
CE(6)
OE
UB, LB
tAA (4)
tACE (4)
tAOE (4)
tABE (4)
R/W
DATAOUT
tLZ (1)
BUSYOUT
Industrial and Commercial Temperature Ranges
tRC
(4)
VALID DATA
tBDD (3,4)
tOH
tHZ (2)
3199 drw 05
Timing of Power-Up Power-Down
CE(6)
tPU
ICC
50%
ISB
tPD
50%
3199 drw 06 .
NOTES:
1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6. Refer to Chip Enable Truth Table.
6.842

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