SC1405BTR データシートの表示（PDF） - Semtech Corporation

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SC1405BTR

HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER

Semtech Corporation 

HIGH SPEED SYNCHRONOUS POWER

MOSFET SMART DRIVER

SC1405B

March 14, 2000

APPLICATION INFORMATION:

SC1405B is the newest and the higher speed version

of the SC1405TS. It is designed to drive Low Rds_On

power MOSFET’s with ultra-low rise/fall times and

propagation delays. As the switching frequencies of

PWM controllers is increased to reduce power supply

and Class-D amplifier volume and cost, fast rise and

fall times are necessary to minimize switching losses

(TOP MOSFET) and reduce Dead-time (BOTTOM

MOSFET). While Low Rds_On MOSFET’s present a

power saving in I2R losses, the MOSFET’s die area is

larger and thus the effective input capacitance of the

MOSFET is increased. Often a 50% decrease in

Rds_On more than doubles the effective input gate

charge, which must be supplied by the driver. The

Rds_On power savings can be offset by the switching

and dead-time losses with a sub-optimum driver.

While discrete solution can achieve reasonable drive

capability, implementing shoot-through, programmable

delay and other housekeeping functions necessary for

safe operation can become cumbersome and costly.

The SC1405 family of parts presents a total solution for

the high-speed, high power density applications. Wide

input supply range of 4.5V-25V allows use in battery

powered applications, new high voltage, distributed

power servers as well as Class-D amplifiers.

THEORY OF OPERATION

The control input (CO) to the SC1405B is typically sup-

plied by a PWM controller that regulates the power

supply output. (See Application Evaluation Schematic,

Figure 3). The timing diagram demonstrates the se-

quence of events by which the top and bottom drive

signals are applied. The shoot-through protection is

implemented by holding the bottom FET off until the

voltage at the phase node (intersection of top FET

source, the output inductor and the bottom FET drain)

has dropped below 1V. This assures that the top FET

has turned off and that a direct current path does not

exist between the input supply and ground, a condition

which both the top and bottom FET’s are on momen-

tarily. The top FET is also prevented from turning on

until the bottom FET is off. This time is internally set to

20ns (typical) and may be increased by adding a ca-

pacitor to the C-Delay pin. The delay is approximately

1ns/pf in addition to the internal 20ns delay. The exter-

nal capacitor may be needed if multiple High input ca-

pacitance MOSFET’s are used in parallel and the fall

time is substantially greater than 20ns.

It must be noted that increasing the dead-time by high

values of C-Delay capacitor will reduce efficiency since

the parallel Shottkey or the bottom FET body diode will

have to conduct during dead-time.

LAYOUT GUIDELINES

As with any high speed , high current circuit, proper

layout is critical in achieving optimum performance of

the SC1405B. The Evaluation board schematic (Refer

to figure 3) shows a dual phase synchronous design

with all surface mountable components.

While components connecting to C-Delay, OVP_S,

EN,S-MOD, DSPS_DR and PRDY are relatively non-

critical, tight placement and short,wide traces must be

used in layout of The Drives, DRN, and especially

PGND pin. The top gate driver supply voltage is pro-

vided by bootstrapping the +5V supply and adding it

the phase node voltage (DRN). Since the bootstrap

capacitor supplies the charge to the TOP gate, it must

be less than .5” away from the SC1405. Ceramic X7R

capacitors are a good choice for supply bypassing near

the chip. The Vcc pin capacitor must also be less than

.5” away from the SC1405. The ground node of this

capacitor, the SC1405 PGND pin and the Source of

the bottom FET must be very close to each other,

preferably with common PCB copper land and multiple

vias to the ground plane (if used). The parallel Shot-

tkey must be physically next to the Bottom FETS Drain

and source. Any trace or lead inductance in these con-

nections will drive current way from the Shottkey and

allow it to flow through the FET’s Body diode, thus re-

ducing efficiency.

PREVENTING INADVERTENT BOTTOM FET

TURN-ON

At high input voltages, (12V and greater) a fast turn-on

of the top FET creates a positive going spike on the

Bottom FET’s gate through the Miller capacitance,

Crss of the bottom FET. The voltage appearing on the

gate due to this spike is:

Vspike=Vin*crss/(Crass+ciss)

Where Ciss is the input gate capacitance of the bottom

FET. This is assuming that the impedance of the drive

path is too high compared to the instantaneous

impedance of the capacitors. (since dV/dT and thus

the effective frequency is very high). If the BG pin of

the SC1405B is very close to the bottom FET, Vspike

will be reduced depending on trace inductance, rate if

rise of current,etc.

© 2000 SEMTECH CORP.

9

652 MITCHELL ROAD NEWBURY PARK CA 91320

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