V437464E24VXTG-75 データシートの表示（PDF） - Mosel Vitelic, Corp
部品番号
コンポーネント説明
一致するリスト
V437464E24VXTG-75 Datasheet PDF : 13 Pages
| |||
MOSEL VITELIC
SPD-Table for modules: (Continued)
Byte
Number
28
29
30
31
32
33
34
35
62-61
62
63
64
65-71
72
73-90
91-92
93
94
95-98
99-125
126
127
128+
Function Described
Minimum Row Active to Row Active Delay
tRRD
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (Per Bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Fu-
ture)
SPD Revision
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
Module Part Number (ASCII)
PCB Identification Code
Assembly Manufacturing Date (Year)
Assembly Manufacturing Date (Week)
Assembly Serial Number
Reserved
Intel Specification for Frequency
Reserved
Unused Storage Location
SPD Entry Value
14 ns/15 ns/16 ns
15 ns/20 ns
42 ns/45 ns
256 MByte
1.5 ns/2.0 ns
0.8 ns/1.0 ns
1.5 ns/2.0 ns
0.8 ns/1.0 ns
Revision 2/1.2
Mosel Vitelic
V437464E24V
V437464E24V
-75PC
0E
Hex Value
-75
0F
-10PC
10
0F
14
14
2A
2D
2D
40
40
40
15
15
20
08
08
10
15
15
20
08
08
10
00
00
00
02
02
12
2F
74
E2
40
40
40
00
00
00
00
00
00
64
64
64
00
00
00
V437464E24V Rev. 1.0 January 2002
6
Share Link: 