P4C1256 データシートの表示（PDF） - Performance Semiconductor
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P4C1256 Datasheet PDF : 8 Pages
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P4C1256
READ CYCLE NO. 1 (OE CONTROLLED)(1)
ADDRESS
OE
CE
tAA
tOE
(4)
tOLZ
tRC (5)
DATA OUT
tAC
tAC(4)
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
ADDRESS
DATA OUT
tAA
tOH
PREVIOUS DATA VALID
tRC (5)
READ CYCLE NO. 3 (CE CONTROLLED)
tRC
CE
tOH
tOHZ(4)
tHZ (4)
DATA VALID
DATA OUT
ICC
VCC SUPPLY ISB
CURRENT
tAC
tLZ(8)
tPU
tHZ
DATA VALID
tPD
HIGH IMPEDANCE
Notes:
1. WE is HIGH for READ cycle.
2.
CE
1
is
LOW,
CE2
is
HIGH
and
OE
is
LOW
for
READ
cycle.
3.
ADDRESS
must
be
valid
prior
to,
or
coincident
with
CE
1
transition
LOW .
4. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the first
transitioning address.
120
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