W83194R-58A データシートの表示（PDF） - Winbond

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W83194R-58A

100MHZ AGP CLOCK FOR VIA CHIPSET

Winbond 

W83194R-58A

AGP[ 0:1]

SDRAM11/

CPU_STOP#

SDRAM10/

PCI_STOP#

SDRAM [ 0:9]

PCICLK_F/ *FS1

PRELIMINARY

15,47

17

18

20,21,28,29,31

,32,34,

35,37,38

7

OUT

I/O

I/O

O

I/O

Accelerate Graphic Port clock outputs

If MODE =1 (default), then this pin is a SDRAM clock

buffered output of the crystal. If MODE = 0 , then this

pin is CPU_STOP# input used in power

management mode for synchronously stopping the

all CPU clocks.

If MODE = 1 (default), then this pin is a SDRAM

clock output. If MODE = 0 , then this pin is

PCI_STOP # and used in power management mode

for synchronously stopping the all PCI clocks.

SDRAM clock outputs which have the same

frequency as CPU clocks.

Latched input for FS1 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks.

Free running PCI clock during normal operation.

Publication Release Date: Nov. 1999

-4-

Revision 0.30

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