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Preliminary W6662CF
Analog
input
CDSCK1
CDSCK2
ADCCLK
DOUT
(PIXn)
(PIXn+1)
(PIXn+2)
(PIXn+3)
(PIXn+4)
tADCL
tACD
tS2AD
tSPD
tCVR
(PIXn-5)
tADCH
(PIXn-4)
Latency
tDOD
0
(PIXn-3)
(PIXn-2)
1
Fig. 7-2 Timing of S&H Mode.
(PIXn-1)
2
(PIXn)
3
ADCCLK
DOUT
OEN
tDOD
tODZ
high-Z
tOED
Fig. 7-3 Output Enable Timing.
SCLK
tSIS
SDI/
SDIO
tSIH
A0 A1 A2
1/fSCLK
tSIS
tSIH
D0 D1 D2 D3 D4 D5 D6 D7
SEN
tSES
tSEH
Fig. 7-4 Serial Interface Write Timing (3-wired or 4-wired Interface).
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