V437464S24VXTG-75 データシートの表示（PDF） - Mosel Vitelic Corporation
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V437464S24VXTG-75
Mosel Vitelic Corporation
V437464S24VXTG-75 Datasheet PDF : 12 Pages
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MOSEL VITELIC
V437464S24V
SPD-Table : (Continued)
Byte Num-
ber
Function Described
28
Minimum Row Active to Row Active Delay
tRRD
29
Minimum RAS to CAS Delay tRCD
30
Minimum RAS Pulse Width tRAS
31
Module Bank Density (Per Bank)
32
SDRAM Input Setup Time
33
SDRAM Input Hold Time
34
SDRAM Data Input Setup Time
35
SDRAM Data Input Hold Time
62-61
Superset Information (May be used in Fu-
ture)
62
SPD Revision
63
Checksum for Bytes 0 - 62
64
Manufacturer’s JEDEC ID Code
65-71 Manufacturer’s JEDEC ID Code (cont.)
72
Manufacturing Location
73-90 Module Part Number (ASCII)
91-92 PCB Identification Code
93
Assembly Manufacturing Date (Year)
94
Assembly Manufacturing Date (Week)
95-98 Assembly Serial Number
99-125 Reserved
126
Intel Specification for Frequency
127
Reserved
128+
Unused Storage Location
SPD Entry Value
14 ns/15 ns/16 ns
15 ns/20 ns
42 ns/45 ns
256 MByte
1.5 ns/2.0 ns
0.8 ns/1.0 ns
1.5 ns/2.0 ns
0.8 ns/1.0 ns
Revision 2/1.2
Mosel Vitelic
V437464S24V
DC Characteristics
TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V
Symbol Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
VOH
Output High Voltage (IOUT = –4.0 mA)
-75PC
0E
Hex Value
-75
0F
0F
14
2A
2D
40
40
15
15
08
08
15
15
08
08
00
00
02
02
10
8C
40
40
00
00
00
00
64
64
00
00
00
00
Limit Values
Min.
Max.
2.0
–0.5
VCC+0.3
0.8
2.4
—
-10PC
10
14
2D
40
20
10
20
10
00
12
C3
40
00
00
64
00
00
Unit
V
V
V
V437464S24V Rev. 1.0 January 2002
5
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