TRU050-GECHA データシートの表示（PDF） - Vectron International
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TRU050-GECHA Datasheet PDF : 15 Pages
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TRU050, VCXO Based PLL
Layout Considerations
To achieve stable, low noise performance good analog layout techniques should be incorporated and a
partial list includes:
The TRU050 should be treated more like an analog device and the power supply should be well decoupled
with good quality RF 0.01 uf and 0.1uf capacitors. In some cases, a pi filter such as a large capacitor (10uF)
to ground, a series ferrite bead or inductor, and 0.01 uf and 100 pf capacitor to ground to decouple the
device supply is used.
The traces for the OUT1, OUT2, RCLK and RDATA ouputs should be kept as short as possible. It is common
practice to use a series resistor – 50 to 100 ohms – in order to reduce reflections if these traces are more
than a couple of inches long. Also OUT1, OUT2 RCLK and RDATA should not be routed directly underneath
the device.
The op-amp loop filter components should be kept as close to the device as possible and the feedback
capacitor should be located close the op-amp input terminal. The loop filter capacitor(s) should be low
leakage and polarized capacitors are allowed keeping this is mind.
Unused outputs should be left floating and it is not required to load or terminate them (such as an PECL or
ECL output). Loading unused outputs will only increase current consumption.
Typical Application Circuits
10K 0.1uF 10K 2.2uF 330K 20K 0.1uF
8 kHz (Pin 7)
pin 6
pin 2
pin 3 pin 1
∅
16kHz (Pin 9)
pin 4
TRU050
10K
10K , 2.2uF
pin 15
44.736 MHz
÷ 2796
The above loop has a 11 Hz bandwidth.
Figure 8. 8kHz to DS3 Frequency Translation
Vectron International, 267 Lowell Rd, Hudson NH 03051-4916
Page 9 of 15
Tel: 1-88-VECTRON-1 • Web: www.vectron.com
Rev: 12Aug2009
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