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RMDA20420 データシートの表示(PDF) - Fairchild Semiconductor

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RMDA20420
Fairchild
Fairchild Semiconductor Fairchild
RMDA20420 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
5 MIL THICK
ALUMINA
50
RF INPUT
10,000pF
Vg2 alt
Vd1
Vd
(Positive) INTERCHANGEABLE Vd BOND PADS
(Do not use Vd2)
100pF
Die-Attach
80Au/20Sn
Vd2
Vd3
Vd4
5 MIL THICK
ALUMINA
50
L<0.015"
4 places
Vd1
Vg2
2 MIL GAP
100pF
Vg
(Negative)
RF OUTPUT
Vg3
Vg4
INTERCHANGEABLE Vg BOND PADS
L<0.015"
10,000pF
Notes:
1. Die-attach with 80Au/20Sn.
2. Use 0.003" x 0.0005" gold ribbon for bonding.
3. RF input and output bonds should be less than 0.015" long with stress relief.
4. For currents > 370 mA connect all drain pads (Vd1, Vd3, & Vd4) to the 100 pF capacitor.
5. Back of chip is DC and RF ground.
6. Do not use Vd2 pad for drain bias connection.
Figure 4. Recommended Assembly and Bonding Diagram
Recommended Procedure (for biasing and operation)
CAUTION: LOSS OF GATE VOLTAGE (Vg) WHILE
DRAIN VOLTAGE (Vd) IS PRESENT CAN DAMAGE THE
AMPLIFIER.
The following sequence must be followed to properly test
the amplifier:
Step 4: Adjust gate bias voltage to set the quiescent current
of Idq = 350 mA.
Step 5: After the bias condition is established, the RF input
signal may now be applied at the appropriate frequency
band.
Step 1: Turn off RF input power.
Step 6: Follow turn-off sequence of:
Step 2: Connect the DC supply grounds to the ground of
the chip carrier. Slowly apply negative gate bias supply
voltage of -1.5V to Vg.
(i) Turn off RF input power,
(ii) Turn down and off drain voltage (Vd),
(iii) Turn down and off gate bias voltage (Vg).
Step 3: Slowly apply positive drain bias supply voltage of
+3.5V to Vd.
©2004 Fairchild Semiconductor Corporation
RMDA20420 Rev. D

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