RH56D-PCI データシートの表示（PDF） - Unspecified
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RH56D-PCI Datasheet PDF : 60 Pages
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RH56D-PCI Modem Designer’s Guide
5.1.19 0x42 - PMC - Power Management Capabilities
The Power Management Capabilities register is a 16-bit read-only register which provides information on the capabilities of
the function related to power management (Table 5-4).
Bit
2:0
3
4
5
8:6
9
10
15:11
R/W
R
R
R
R
R
R
R
R
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Description
Version. 010b indicates compliance with Revision 1.0 of the PCI Power Management Interface
Specification.
PME Clock. Hard coded to 0 to indicate that the PCI clock is not required for PME generation .
Reserved (=0b).
DSI (Device Specific Initialization). Loaded from serial EEPROM.
Aux. Current. Loaded from serial EEPROM.
D1_Support. When set to a 1, the BIF device supports D1 power state (loaded from serial EEPROM).
D2_ Support. When set to a 1, the BIF device supports D2 power state (loaded from serial EEPROM).
These 5 bits indicate which power states allow assertion of PME (loaded from serial EEPROM). A value of
0b for any bit indicates that the function cannot assert the PME# signal while in that power state.
Bit 11: 1 = PME# can be asserted from D0
Bit 12: 1 = PME# can be asserted from D1
Bit 13: 1 = PME# can be asserted from D2
Bit 14 1 = PME# can be asserted from D3hot
Bit 15 1 = PME# can be asserted from D3cold.
5.1.20 0x44 - PMCSR - Power Management Control/Status Register (Offset = 4)
This 16-bit register is used to manage the PCI function’s power management state as well as to enable/monitor power
management events (Table 5-5).
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Bit
R/W
Description
1:0
R/W Power State.
7:2
8
12:9
14:13
00 = D0
01 = D1
10 = D2
11 = D3.
R
Reserved (= 000000b).
R/W PME_En. A 1 enables PME assertion.
R/W Data_Select. Selects Data and Data Scale fields.
R
Data Scale. Associated with Data field. Loaded from serial EEPROM.
15:11
R/C PME_Status. This bit is sticky when PME assertion from D3_COLD is supported.
PME_Status = 1 indicates PME asserted by the BIF device. Writing 1 clears PME_Status. Writing 0 has
no effect.
R: Bit(s) is (are) read only.
R/W: Bit(s) is (are) readable and writeable.
R/C: Bit(s) is (are) readable, and clearable by writing 1 (bit may not be set by writing).
5.1.21 0x46 - PMCSR_BSE - PMCSR PCI to PCI Bridge Support Extensions
PMCSR_BSE is cleared to 0 to indicate that bus power/clock control policies have been disabled.
5.1.22 0x47 - Data
This register is used to report the state dependent data requested by the Data_Select field. The value of this register is scaled
by the value reported by the Data_Scale field.
5-4
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