ML6691 データシートの表示（PDF） - Micro Linear Corporation
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ML6691 Datasheet PDF : 10 Pages
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ML6691
MANAGEMENT SECTION
The ML6691 implements the applicable portions of the
IEEE 802.3 Control and Status registers. The management
section provides a two-wire serial interface for the
purpose of control and status gathering. The MDIO pin is
a bi-directional signal used to transfer control information
between the ML6691 and the MAC. Data on MDIO is
clocked using the MDC pin. The following frame structure
is used:
PRE ST OP PHYAD REGAD TA
READ 1 01 10 AAAAA RRRRR Z0
WRITE 1 01 01 AAAAA RRRRR 10
DATA
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
IDLE
Z
Z
PRE (Preamble)
The preamble condition on the two wire interface is a
logic one. Prior to initiation of any other transaction, a
sequence of 32 consecutive logic ones must be presented
on MDIO with 32 corresponding cycles on MDC to
establish synchronization.
ST (Start of Frame)
The start of frame is indicated by a <01> pattern. This
pattern assures transitions from the default logic one line
state to zero and back to one.
OP (Operation Code)
The operation code for a read transaction is <10>, while
the operation code for a write transaction is <01>.
PHYAD (PHY Address)
The PHY Address is five bits, allowing 32 unique PHY
addresses. The first PHY address bit transmitted and
received is the MSB of the address.
REGAD (Register Address)
The Control register is address <00000>, and the Status
register is address <00001>.
TA (Turnaround)
The turnaround time is a 2 bit time spacing between the
Register Address field and the Data field of a management
frame to avoid contention during a read transaction.
DATA (Data)
The data field is 16-bits. The first data bit transmitted and
received shall be bit 15 of the register being addressed.
CONTROL REGISTER
Table 2 shows the applicable portions of the Control
registers that are implemented in the ML6691. Bits 12, 9,
and 6–0 are read-only and have default values of logic
low.
CONTROL REGISTER
BIT
NAME
DESCRIPTION
15
Reset
14
Loopback
13
Speed Selection
11
Power Down
10
Isolate
8
Duplex Mode
7
Collision Test
1 = reset
0 = normal operation
1 = loopback
0 = normal operation
1 = 100Mb/s
0 = 10Mb/s
1 = power down
0 = normal operation
1= electrically isolate from MII
0 = normal operation
1 = full duplex
0 = half duplex
1 = test Col signal
0 = normal operation
NOTE: R/W = Read/Write, SC = Self Clearing
Table 2. Control Register
R/W
R/W
SC
R/W
R
R/W
R/W
R/W
R/W
DEFAULT
0
0
1
0
Determined by LOCAL
0
0
8
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