![](/html/Infineon/765339/page16.png)
1.5 Functional Block Diagram
DCL / SCL
FSC / DIR
DD0 / SIP0
DU0 / SIP4
DD1 / SIP1
DU1 / SIP5
DD2 / SIP2
DU2 / SIP6
DD3 / SIP3
DU3 / SIP7
Layer 1
Controller
Buffer
RES
Timer
Data Memory
Control Memory
µ P Interface
AD7...0 WR RD ALE CS INT A3...0
Figure 5
Functional Block Diagram EPIC®
PEB 2055
PEF 2055
Overview
PDC
PFS
RxD0
TxD0
TSC0
RxD1
TxD1
TSC1
RxD2
TxD2
TSC2
RxD3
TxD3
TSC3
ITB09533
Semiconductor Group
16