3335-00 データシートの表示（PDF） - Peregrine Semiconductor Corp.

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3335-00

3000 MHz UltraCMOS™ Integer-N PLL for Low Phase Noise Applications

Peregrine Semiconductor Corp. 

PE3335

Product Specification

Functional Description

The PE3335 consists of a prescaler, counters, a

phase detector, a charge pump and control logic.

The dual modulus prescaler divides the VCO

frequency by either 10 or 11, depending on the

value of the modulus select. Counters “R” and “M”

divide the reference and prescaler output,

respectively, by integer values stored in a 20-bit

register. An additional counter (“A”) is used in

the modulus select logic. The phase-frequency

Figure 3. Functional Block Diagram

detector generates up and down frequency control

signals. The control logic includes a selectable

chip interface. Data can be written via serial bus,

parallel bus, or hardwired direct to the pins. There

are also various operational and test modes and

lock detect.

fr

R Counter

fc

(6-bit)

D(7:0)

Sdata

Control

Pins

Control

Logic

R(5:0)

M(8:0)

A(3:0)

Modulus

Select

Fin

10/11

Fin

Prescaler

M Counter

(9-bit)

Phase

Detector

PD_U

Charge

PD_D Pump

CP

LD

Cext

2 kΩ

fp

Document No. 70-0049-02 │ www.psemi.com

©2005 Peregrine Semiconductor Corp. All rights reserved.

Page 7 of 15

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