MC68194FJ データシートの表示（PDF） - ON Semiconductor

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MC68194FJ

Carrier Band Modem (CBM)

ON Semiconductor 

MC68194

3.3 JABBER INHIBIT

The jabber inhibit function prevents the transmitter from

transmitting indefinitely. An external resistor and capacitor

pair tied to the CBM JAB–RC pin set the maximum time that

the transmitter is allowed to transmit. When transmission is

attempted for a period longer than the specified time, the

jabber inhibit function forces the transmitter to shut down

and alerts the system that this has been done by generating

a PHYSICAL ERROR indication on the serial interface

indication channel. The error indication is removed only

after a reset has occurred on the RESET pin or after a RESET

command has been received on the station management

interface. The ENABLE TRANSMITTER and DISABLE

LOOPBACK commands can then be used to re–enable the

transmitter outputs. While the PHYSICAL ERROR

indication is present, the normally–low JAB pin of the

MC68194 will be high. This TTL output may be used to turn

off external transmitter circuitry or an isolation relay.

A block diagram of the jabber inhibit function is shown in

Figure 3–3. When edges are present on the TXDATA line,

the jabber capacitor is allowed to charge. When the

transmitter stops transmitting, the capacitor is discharged.

The circuit looks for any edges in the previous 16 TXCLKs

before deciding whether to charge or discharge the

capacitor. When the capacitor voltage reaches the reference

threshold, the comparator switches and the jabber output is

latched. The jabber output is fed back internally and disables

the transmitter. This signal is also brought out to the JAB pin

for use in disabling external transmitter circuitry.

For the IEEE 802.4 spec, the jabber timeout must be 0.5

sec ± 25%. An RC time constant of 265 millisec. will give

about a 0.5 sec timeout. The maximum resistor size is 125

kΩ. Components should be 10% tolerance or better.

Common values are R = 120 kΩ and C = 2.2 µF.

3.4 CLOCK GENERATOR

The clock generator is used to generate all of the transmit

timing, TXCLK, and internal CBM timing for station

B B management and loopback. The generator consists of a

crystal oscillator/buffer that drives 2 and 4 stages. The

oscillator frequency must be four times (4X) the serial data

rate. As an example, the IEEE 802.4 5 Mbps carrier band

(TXCLK = 5.0 MHz) requires an oscillator frequency of 20

MHz. The basic circuit is a single transistor Colpitts

oscillator as shown in Figure 3–4.

The oscillator is used in one of three modes depending on

the data rate and the application:

1. With a parallel–resonant, fundamental mode crystal.

2. With a parallel–resonant, overtone mode crystal.

3. With an external clock source.

The fundamental mode can typically be used up to

frequencies of about 20 MHz; this is crystal dependent and

some crystal types can be used as high as 40 MHz. Beyond

the fundamental mode upper limit, an overtone mode crystal

is used. An alternative to a crystal is an external clock source

such as an integrated crystal clock to drive the CBM.

3.4.1 Parallel–Resonant, Fundamental Mode Crystal

Figure 3–4 shows the external crystal and capacitors C1

and C2 used for fundamental mode operation. The crystal

must be parallel resonant with a maximum series resistance

of 30 Ω.

This configuration is normally used for the IEEE 802.4

5 Mbps carrierband standard. The required transmit

frequency stability is ± 100 ppm (0.01%). It is suggested that

a crystal with a total frequency tolerance (calibration

tolerance, temperature variation, plus aging) of ± 50 ppm to

± 60 ppm be used. The remaining frequency budget is

reserved for the CBM and other components over

temperature and power supply variation.

The series combination of C1 and C2 should be equal to

the specified crystal load (typically 20 pF or 32 pF).

Additionally, C1 and C2 should be large enough to swamp

out the CBM device capacitance. The XTAL1 input

capacitance is typically 1.5 pF to 2.0 pF, and C1 should be

at least an order of magnitude greater (C1 > 20 pF). Also, C1

must be greater than the crystal load capacitance because of

the series combination of C1 and C2. Generally the ratio

C1:C2 is from 1:1 to 3:1.

+5V

DQ

TXDATA

CLK

R

R JAB

VCC

JAB RC

PIN

D

CLK

Q

C JAB

+

–

JAB PIN

+ 5V

DQ

CLK

R

DELAY

V REF

PHYSICAL MANAGEMENT

OR HARDWARE RESET

TXCLK

ONE OF 16

Figure 3–3. Jabber Inhibit Block Diagram

INTERNAL

JABBER INHIBIT

http://onsemi.com

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