M62392P データシートの表示（PDF） - Renesas Electronics

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M62392P

8-bit 12ch I2C BUS D/A Converter with Buffer Amplifiers

Renesas Electronics 

M62392P/FP

Timing Chart (Model)

<Start condition to slave address bite>

Preliminary

SDA

1

2

3

4

5

6

7

W

A

SCL

R

D/A

output

Start condition

<Sub address bite>

SDA

1

2

3

4

5

6

7

8

A

SCL

R

D/A

output

<DAC data bite to stop condition>

SDA

1

2

3

4

5

6

7

8

A

SCL

R

D/A

output

Stop condition

 Start condition: With SCL at high, SDA line goes from high to low

 Stop condition: With SCL at high, SDA line goes from low to high

(Under normal circumstances, SDA is changed when SCL is low)

 Acknowledge bit: The receiving IC has to pull down SDA line whenever receive slave data.

(The transmitting IC releases the SDA line just then transmit 8-bit data.)

R03DS0045EJ0400 Rev.4.00

Jun 03, 2011

Page 6 of 8

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