LZ9GF16 データシートの表示（PDF） - Sharp Electronics

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LZ9GF16

LZ 9 G Series 1 6 0 0 Gates Gate Array

Sharp Electronics 

SHARP

LZSGjF16

7

7. Condition for signal input

7-l In case of using PLL circuit (CLKC=H)

Clock input : OSCI -

Parameter

Symb1o

min

UP

Input frequency

l/To

9.4

Duty ratio

TOL~M

40160

so/50

Composite (Horizontal) sync. signal (Positive) : SW1

Input condition

Baseon NTSC(Ms)ystem

Base on PUB, 3) system

max

60140

unit remarks

MHZ

%

remarks

NTPC=H

NTPC=L

I

16

fsm125a ~MZ

f &304

kIi!?l

600

PS

58

PS

Timing of VIN input to be specified. (See fig. 2-h)

fsyn=SYNI (composite sync. signal) input frequency (unit : kHz)

(Note31

In case of no VIN input, vertical counter inside of IC is reset

automatically based on f&284 (NTPC=H),fsun/344(NTPC=L).

(Note41

After VSYfalling, VIN input is invalid during the period of

192H(NTPC=H)2,27H(NTPC=L).(lH=l/ fm)

However, the case of VSYfalling by automatic reset is exceptional.

Input LOWI,RESHand RESV

Input VDI,through and integration circuit(Contro1 circuitry example : refernces)

with following value(z ,),

or please input the Low level after VD--D_tu_r_ning __o_n__by this period systemreset.

jSymbol---

min

tYP---~~--~.ioo~aax---- , Unit 1

i

T”

20

ms _J

NTPC=H

NTPC=L

(Note11

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