IS61LV6464(2004) データシートの表示（PDF） - Integrated Silicon Solution

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IS61LV6464
(Rev.:2004)

64K x 64 SYNCHRONOUS PIPELINE STATIC RAM

Integrated Silicon Solution 

IS61LV6464

READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

Symbol Parameter

-100

Min. Max.

tKC

Cycle Time

10 —

tKH

Clock High Time

4—

tKL

Clock Low Time

4—

tKQ

Clock Access Time

—5

tKQX(1) Clock High to Output Invalid

2.5 —

tKQLZ(1,2) Clock High to Output Low-Z

0—

tKQHZ(1,2) Clock High to Output High-Z

2

5

tOEQ

Output Enable to Output Valid

—5

tOEQX(1) Output Disable to Output Invalid

0—

tOELZ(1,2) Output Enable to Output Low-Z

0—

tOEHZ(1,2) Output Disable to Output High-Z

2

5

tAS

Address Setup Time

2.5 —

tSS

Address Status Setup Time

2.5 —

tWS

Write Setup Time

2.5 —

tCES

Chip Enable Setup Time

2.5 —

tAVS

Address Advance Setup Time

2.5 —

tAH

Address Hold Time

0.5 —

tSH

Address Status Hold Time

0.5 —

tWH

Write Hold Time

0.5 —

tCEH

Chip Enable Hold Time

0.5 —

tAVH

Address Advance Hold Time

0.5 —

Note:

1. Guaranteed but not 100% tested. This parameter is periodically sampled.

2. Tested with load in Figure 2.

-6

Min. Max.

12 —

4.5 —

4.5 —

—6

2.5 —

0—

2

5

—5

0—

0—

2

5

2.5 —

2.5 —

2.5 —

2.5 —

2.5 —

0.5 —

0.5 —

0.5 —

0.5 —

0.5 —

ISSI ®

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Integrated Silicon Solution, Inc. — 1-800-379-4774

9

Rev. B

01/15/04

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