IS61C6416 データシートの表示（PDF） - Integrated Silicon Solution

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IS61C6416

64K x 16 HIGH-SPEED CMOS STATIC RAM

Integrated Silicon Solution 

IS61C6416

WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2)

t WC

ADDRESS

VALID ADDRESS

OE

ISSI ®

t HA

CE LOW

WE

UB, LB

t SA

DOUT

DATA UNDEFINED

DIN

t AW

t PWE1

t PBW

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DATAIN VALID

WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1)

t WC

ADDRESS

VALID ADDRESS

OE LOW

t HA

UB_CEWR2.eps

CE LOW

WE

t SA

t AW

t PWE2

t PBW

UB, LB

DOUT

DATA UNDEFINED

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DIN

DATAIN VALID

UB_CEWR3.eps

Notes:

1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if OE ≥ VIH.

8

Integrated Silicon Solution, Inc. — 1-800-379-4774

SR005-1D

05/24/99

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