CS5231-3GDF8 データシートの表示（PDF） - ON Semiconductor
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CS5231-3GDF8 Datasheet PDF : 14 Pages
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CS5231−3
First, we determine the need for heatsinking. If we assume
the maximum qJA = 50 °C/W for the D2PAK, the maximum
temperature rise is found to be
DT + PD qJA + 1.018 W 50°CńW + 50.9°C
This is less than the maximum specified operating
junction temperature of 125°C, and no heatsinking is
required. Since the D2PAK has a large tab, mounting this
part to the PC board by soldering both tab and leads will
provide superior performance with no PC board area
penalty.
TYPICAL FUSED SOIC−8 DESIGN
We first determine the need for a heat sink for the SOIC−8
package at a load of 500 mA. Using the dissipation from the
D2PAK example of 1018 mW and the qJA of the SOIC−8
package of 110°C/W gives a temperature rise of 112°C.
Adding this to an ambient temperature of 70°C gives 182°C
junction temperature. This is an excessive temperature rise
but it can be reduced by adding additional cooling in the
form of added surface area of copper on the PCB. Using the
relationship of maximum temperature rise of
DTJA + TJ(MAX) * TA + 150°C * 70°C + 80°C
We calculate the thermal resistance allowed from junction
to air:
qJA(worst case) + DTJAńPD + 80°Cń1.018 W + 79.6°CńW
The thermal resistance from the die to the leads (case) is
25°C/W. Subtracting these two numbers gives the allowable
thermal resistance from case to ambient:
qCA + qJA * qJC + 79.6°CńW * 25°CńW + 54.6°CńW
The thermal resistance of this copper area will be
54.6°C/W. We now look at Figure 20 and find the PCB trace
area that will be less than 54.5°C/W. Examination shows that
750 mm2 of copper will provide cooling for this part. This
would be the SOIC−8 part with the center 4 ground leads
soldered to pads in the center of a copper area about 27 mm
× 27 mm. A lower dissipation or the addition of air−flow
could result in a smaller required surface area.
DESCRIPTION
The CS5231−3 application circuit has been implemented
as shown in the following pages. The schematic, bill of
materials and printed circuit board artwork can be used to
build the circuit. The design is very simple and consists of
two capacitors, a p−channel FET and the CS5231−3. Five
turret pins are provided for connection of supplies, meters,
oscilloscope probes and loads. The CS5231−3 power supply
management solution is implemented in an area less than 1.5
square inches. Due to the simplicity of the design, output
current must be derated if the CS5231−3 is operated at VIN
voltages greater than 7.0 V. Figure 21 provides the derating
curve on a maximum power dissipation if heatsink is added.
Operating at higher power dissipation without CS5231−3
heatsink may result in a thermal shutdown condition.
600
500
400
300
200
100
0
5 6 7 8 9 10 11 12 13 14
VIN (Volts)
Figure 21. Demo Board Output Current
Derating vs. VIN
The VIN Connection
The VIN connection is denoted as such on the PC board.
The maximum input voltage to the IC is 14 V before damage
to the IC is possible. However, the specification range for the
IC is 4.75 V < VIN < 6.0 V.
The GND Connection
The GND connection ties the IC power return to two turret
pins. The extra turret pin provides for connection of multiple
instrument grounds to the demonstration board.
The AuxDrv Connection
The AuxDrv lead of the CS5231−3 is connected to the gate
of the external PFET. This connection is also brought to a
turret pin to allow easy connection of an oscilloscope probe
for viewing the AuxDrv waveforms.
The VAUX Connection
The VAUX turret pin provides a connection point between
an external 3.3 V supply and the PFET drain.
The VOUT Connection
The VOUT connection is tied to the VOUT lead of the
CS5231−3 and the PFET source. This point provides a
convenient point at which some type of lead may be applied.
VIN TP1
C1
GND
TP2
TP3
VIN
VOUT U1
CS5231−3
GND AuxDrv
Q1
TP4
+3.3 V VAUX
C2
TP5
TP6
AuxDrv
Figure 22. Application Circuit Schematic
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