82559ER データシートの表示（PDF） - Intel

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コンポーネント説明

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82559ER

Fast ethernet PCI controller

Intel 

Networking Silicon — GD82559ER

• ISOLATE# trailing edge

The internal initialization signal resets the PCI Configuration Space, MAC configuration, and

memory structure.

The behavior of the PCI RST# signal and the internal 82559ER initialization signal are shown in

the figure below.

PCI RST#

Internal hardware

reset

D0 - D2 power state

PCI RST#

Internal hardware

reset

ISOLATE#

Internal hardware

reset

D3 power state

640 ns

Internal reset

due to ISOLATE#

640 ns

Figure 10. 82559ER Initialization upon PCI RST# and ISOLATE#

4.2.5

Wake-up Events

There are two types of wake-up events: “Interesting” Packets and Link Status Change. These two

events are detailed below.

Note: The wake-up event is supported only if the PME Enable bit in the Power Management Control/

Status (PMCSR) register is set. (The PMCSR is described in Section 7.1.19, “Power Management

Control/Status Register (PMCSR)” on page 55.)

4.2.5.1

“Interesting” Packet Events

In the power-down state, the 82559ER is capable of recognizing “interesting” packets. The

82559ER supports pre-defined and programmable packets that can be defined as any of the

following:

• ARP Packets (with Multiple IP addresses)

• Direct Packets (with or without type qualification)

• Neighbor Discovery Multicast Address Packet (‘ARP’ in IPv6 environment)

• NetBIOS over TCP/IP (NBT) Query Packet (under IPv4)

• Internetwork Package Exchange* (IPX) Diagnostic Packet

This allows the 82559ER to handle various packet types. In general, the 82559ER supports

programmable filtering of any packet in the first 128 bytes.

Datasheet

27

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