AX88796L データシートの表示（PDF） - Unspecified
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AX88796L Datasheet PDF : 71 Pages
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AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
FIGURES
FIG - 1 AX88796 BLOCK DIAGRAM ............................................................................................................................. 5
FIG - 2 AX88796 PIN CONNECTION DIAGRAM.............................................................................................................. 6
FIG - 3 AX88796 PIN CONNECTION DIAGRAM WITH SPP PORT OPTION......................................................................... 7
FIG - 4 AX88796 PIN CONNECTION DIAGRAM FOR ISA BUS MODE ............................................................................... 8
FIG - 5 AX88796 PIN CONNECTION DIAGRAM FOR 80X86 MODE .................................................................................. 9
FIG - 6 AX88796 PIN CONNECTION DIAGRAM FOR MC68K MODE.............................................................................. 10
FIG - 7 AX88796 PIN CONNECTION DIAGRAM FOR MCS-51 MODE ............................................................................. 11
FIG - 8 RECEIVE BUFFER RING.................................................................................................................................... 22
FIG - 9 RECEIVE BUFFER RING AT INITIALIZATION ...................................................................................................... 23
TABLES
TAB - 1 LOCAL CPU BUS INTERFACE SIGNALS GROUP.................................................................................................. 12
TAB - 2 10/100MBPS TWISTED-PAIR INTERFACES PINS GROUP ..................................................................................... 13
TAB - 3 BUILT-IN PHY LED INDICATOR PINS GROUP .................................................................................................. 13
TAB - 4 EEPROM BUS INTERFACE SIGNALS GROUP..................................................................................................... 14
TAB - 5 MII INTERFACE SIGNALS GROUP..................................................................................................................... 14
TAB - 6 STANDARD PRINTER PORT INTERFACE PINS GROUP ......................................................................................... 15
TAB - 7 GENERAL PURPOSES I/O PINS GROUP.............................................................................................................. 15
TAB - 8 MISCELLANEOUS PINS GROUP......................................................................................................................... 17
TAB - 9 POWER ON CONFIGURATION SETUP TABLE ..................................................................................................... 17
TAB - 10 I/O ADDRESS MAPPING ............................................................................................................................... 18
TAB - 11 LOCAL MEMORY MAPPING .......................................................................................................................... 18
TAB - 12 PAGE 0 OF MAC CORE REGISTERS MAPPING................................................................................................ 32
TAB - 13 PAGE 1 OF MAC CORE REGISTERS MAPPING................................................................................................ 33
TAB - 14 THE EMBEDDED PHY REGISTERS................................................................................................................. 40
TAB - 15 MII MANAGEMENT FRAME FORMAT ............................................................................................................ 53
TAB - 16 MII MANAGEMENT FRAMES- FIELD DESCRIPTION......................................................................................... 53
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ASIX ELECTRONICS CORPORATION
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