AX88796L データシートの表示（PDF） - Unspecified

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AX88796L

3-in-1 Local Bus Fast Ethernet Controller

Unspecified 

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

4.0 Basic Operation

4.1 Receiver Filtering

The address filtering logic compares the Destination Address Field (first 6 bytes of the received packet) to the Physical

address registers stored in the Address Register Array. If any one of the six bytes does not match the pre-programmed

physical address, the Protocol Control Logic rejects the packet. This is for unicast address filtering. All multicast

destination addresses are filtered using a hashing algorithm. (See following description.) If the multicast address indexes

a bit that has been set in the filter bit array of the Multicast Address Register Array the packet is accepted, otherwise it is

rejected by the Protocol Control Logic. Each destination address is also checked for all 1's which is the reserved broadcast

address.

4.1.1 Unicast Address Match Filter

The physical address registers are used to compare the destination address of incoming packets for rejecting or accepting

packets. Comparisons are performed on a byte wide basis. The bit assignment shown below relates the sequence in

PAR0-PAR5 to the bit sequence of the received packet.

PAR0

PAR1

PAR2

PAR3

PAR4

PAR5

D7

DA7

DA15

DA23

DA31

DA39

DA47

D6

DA6

DA14

DA22

DA30

DA38

DA46

D5

DA5

DA13

DA21

DA29

DA37

DA45

D4

DA4

DA12

DA20

DA28

DA36

DA44

D3

DA3

DA11

DA19

DA27

DA35

DA43

D2

DA2

DA10

DA18

DA26

DA34

DA42

D1

DA1

DA9

DA17

DA25

DA33

DA41

D0

DA0

DA8

DA16

DA24

DA32

DA40

Note: The bit sequence of the received packet is DA0, DA1, … DA7, DA8 ….

4.1.2 Multicast Address Match Filter

The Multicast Address Registers provide filtering of multicast addresses hashed by the CRC logic. All destination

addresses are fed through the 32 bits CRC generation logic and as the last bit of the destination address enters the CRC,

the 6 most significant bits of the CRC generator are latched. These 6 bits are then decoded by a 1 of 64 decode to index

a unique filter bit (FB0-63) in the Multicast Address Registers. If the filter bit selected is set, the multicast packet is

accepted. The system designer would use a program to determine which filter bits to set in the multicast registers. All

multicast filter bits that correspond to Multicast Address Registers accepted by the node are then set to one. To accept all

multicast packets all of the registers are set to all ones.

MAR0

MAR1

MAR2

MAR3

MAR4

MAR5

MAR6

MAR7

D7

FB7

FB15

FB23

FB31

FB39

FB47

FB55

FB63

D6

FB6

FB14

FB22

FB30

FB38

FB46

FB54

FB62

D5

FB5

FB13

FB21

FB29

FB37

FB45

FB53

FB61

D4

FB4

FB12

FB20

FB28

FB36

FB44

FB52

FB60

D3

FB3

FB11

FB19

FB27

FB35

FB43

FB51

FB59

D2

FB2

FB10

FB18

FB26

FB34

FB42

FB50

FB58

D1

FB1

FB9

FB17

FB25

FB33

FB41

FB49

FB57

D0

FB0

FB8

FB16

FB24

FB32

FB40

FB48

FB56

19

ASIX ELECTRONICS CORPORATION

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