AX88796L データシートの表示（PDF） - Unspecified

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AX88796L

3-in-1 Local Bus Fast Ethernet Controller

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AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

2.0 Signal Description

The following terms describe the AX88796 pin-out:

All pin names with the “/” suffix are asserted low.

The following abbreviations are used in following Tables.

I

Input

PU

O

Output

PD

I/O Input/Output

P

OD Open Drain

2.1 Local CPU Bus Interface Signals Group

Pull Up

Pull Down

Power Pin

SIGNAL

SA[9:1],

SA[0]/LDS

/BHE

or

/UDS

SD[15:0]

IREQ/IREQ

RDY/DTACK

/CS

/IORD

/IOWR

or

R/W

/OCS16

AEN

or

/PSEN

TYPE

I

I/PU

I/O/PD

O

OD

I/PU

I/PU

I/PU

OD

I/PD

PIN NO.

15,

12 – 4

22

23 – 26,

29 – 33,

35 – 39,

41 – 42

16

2

128

19

18

123

1

DESCRIPTION

System Address : Signals SA[9:0] are address bus input lines, which

lower I/O spaces on chip. SA[0] also means Lower Data Strobe

(/LDS) active low signal in 68K application mode.

Bus High Enable or Upper Data Strobe : Bus High Enable is active

low signal in some 16-bit application mode, which enable high bus

(SD[15:8]) active. The signal also name as Upper Data Strobe (/UDS)

for 68K application mode.

System Data Bus : Signals SD[15:0] constitute the bi-directional data

bus.

Interrupt Request : When ISA BUS or 80186 CPU mode is select.

IREQ is asserted high to indicate the host system that the chip

requires host software service. When MC68K or MCS-51 CPU mode

is select. /IREQ is asserted low to indicate the host system that the

chip requires host software service.

Ready : This signal is set low to insert wait states during Remote

DMA transfer.

/Dtack : When Motorola CPU type is selected, the pin is active low

inform CPU that data is accepted.

Chip Select

When the /CS signal is asserted, the chip is selected.

I/O Read :The host asserts /IORD to read data from AX88796 I/O

space. When Motorola CPU type is select , the pin is useless.

I/O Write :The host asserts /IOWR to write data into AX88796 I/O

space. When Motorola CPU type is select, the pin is active high for

read operation at the same time.

I/O is 16 Bit Port : The /IOIS16 is asserted when the address at the

range corresponds to an I/O address to which the chip responds, and

the I/O port addressed is capable of 16-bit access.

Address Enable : The signal is asserted when the address bus is

available for DMA cycle. When negated (low), AX88796 an I/O slave

device may respond to addresses and I/O command.

PSEN : This signal is active low for 8051 program access. For I/O

device, AX88796, this signal is active high to access the chip. This

signal is for 8051 bus application only.

Tab - 1 Local CPU bus interface signals group

12

ASIX ELECTRONICS CORPORATION

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