AX88140A データシートの表示（PDF） - Unspecified

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AX88140A

Fast Ethernet MAC Controller

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AX88140A

CONTENTS

PRELIMINARY

1.0 INTRODUCTION ................................................................................................................................................ 6

1.1 GENERAL DESCRIPTION: ...................................................................................................................................... 6

1.2 FEATURES............................................................................................................................................................ 7

1.3 BLOCK DIAGRAM: ............................................................................................................................................... 8

1.4 AX88140AQ PIN CONNECTION DIAGRAM FOR 160-PIN...................................................................................... 9

1.5 AX88140AP PIN CONNECTION DIAGRAM FOR 144-PIN .................................................................................... 10

2.0 SIGNAL DESCRIPTION .................................................................................................................................. 11

2.1 SIGNAL DESCRIPTIONS FOR 160-PIN AND 144-PIN.............................................................................................. 11

2.2 PCI INTERFACE GROUP ...................................................................................................................................... 12

2.3 BOOT ROM , SERIAL ROM , GENERAL-PURPOSE SIGNALS GROUP.................................................................... 14

2.4 MII/SYM/SRL INTERFACE SIGNALS GROUP ...................................................................................................... 14

2.5 EXTENDED , NC, POWER PINS GROUP ................................................................................................................ 16

3.0 CONFIGURATION OPERATION .................................................................................................................. 17

3.1 CONFIGURATION SPACE MAPPING ..................................................................................................................... 17

3.2 CONFIGURATION SPACE..................................................................................................................................... 18

3.2.1 Configuration ID Register (CSID)............................................................................................................ 18

3.2.2 Command and Status Configuration Register (CSCS)............................................................................... 18

3.2.3 Configuration Revision Register (CSRV).................................................................................................. 18

3.2.4 Configuration Latency Timer Register (CSLT)......................................................................................... 18

3.2.5 Configuration Base I/O Address Register (CBIO).................................................................................... 19

3.2.6 Configuration Base Memory Address Register (CBMA) .......................................................................... 19

3.2.7 Expansion ROM Base Address Register (CBER)...................................................................................... 19

3.2.8 Configuration Interrupt Register (CSIT) .................................................................................................. 19

4.0 REGISTERS OPERATION .............................................................................................................................. 20

4.1 REGISTERS MAPPING ......................................................................................................................................... 20

4.2 HOST REGS ....................................................................................................................................................... 21

4.2.1 Bus Mode Register (REG0)........................................................................................................................ 21

4.2.2 Transmit Poll Demand (REG1)................................................................................................................. 21

4.2.3 Receive Poll Demand (REG2)................................................................................................................... 22

4.2.4 Receive List Base Address (REG3) ........................................................................................................... 22

4.2.5 Transmit List Base Address (REG4) ......................................................................................................... 22

4.2.6 Status Register (REG5) ............................................................................................................................. 23

4.2.7 Operation Mode Register (REG6) ............................................................................................................ 24

4.2.8 Interrupt Enable Register (REG7) ............................................................................................................ 26

4.2.9 Missed Frame and Overflow Counter (REG8) ........................................................................................ 26

4.2.10 Serial ROM and MII Management Register (REG9).............................................................................. 27

4.2.11 General-Purpose Timer (REG11)........................................................................................................... 27

4.2.12 General-Purpose Port Register (REG12) ............................................................................................... 28

4.2.13 Filtering Index (REG13) ......................................................................................................................... 28

4.2.14 Filtering data (REG14)........................................................................................................................... 28

5.0 HOST COMMUNICATION.............................................................................................................................. 30

5.1 DESCRIPTOR LISTS AND DATA BUFFERS............................................................................................................ 30

5.2 RECEIVE DESCRIPTORS ...................................................................................................................................... 31

5.2.1 Receive Descriptor 0 (RDES0) .................................................................................................................. 31

5.2.2 Receive Descriptor 1 (RDES1) .................................................................................................................. 32

5.2.3 Receive Descriptor 2 (RDES2) .................................................................................................................. 32

5.2.4 Receive Descriptor 3 (RDES3) .................................................................................................................. 32

5.3 TRANSMIT DESCRIPTORS ................................................................................................................................... 33

5.3.1 Transmit Descriptor 0 (TDES0)................................................................................................................. 33

5.3.2 Transmit Descriptor 1 (TDES1)................................................................................................................. 34

5.3.3 Transmit Descriptor 2 (TDES2)................................................................................................................. 34

5.3.4 Transmit Descriptor 3 (TDES3)................................................................................................................. 34

2

ASIX ELECTRONICS CORPORATION

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