LC7073 データシートの表示（PDF） - SANYO -> Panasonic
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LC7073 Datasheet PDF : 9 Pages
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LC7073, 7073M
COREN and DSTCTL Input Read
COREN and DSTCTL are monitored at intervals of one input clock cycle, and their logic states can be changed at any
time. During sync detection, a change in input state occurs if either pin remains steady for four successive clock intervals
as shown in figure 4.
Figure 4. Input read during sync detection
After sync detection a change in input state occurs if either COREN or DSTCTL remains steady for four successive input
data blocks as shown in figure 5.
Figure 5. Input read after sync detection
Design Notes
Oscillator specifications are shown in table 2 and figure 6. Oscillator stabilization delay is shown in figure 7. Reset input
circuitry is shown in figure 8. Supply rise time versus RES delay is shown in figure 9.
Table 2. Oscillator capacitor values
4 MHz resonator type
Murata-CSA4.00MG
Kyocera-KBR4.0M
C1, C2
30 pF ±10%
30 pF ±10%
OSC1
OSC2
C1
Ceramic
C2
resonator
Figure 6. Oscillator circuit
VDD
OSC
4.5V
0V
tCFS
tCFS is the oscillator stabilization time
Figure 7. Oscillator stabilization delay
No.3932–7/9
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