ADT7310(2009) データシートの表示（PDF） - Analog Devices
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ADT7310 Datasheet PDF : 24 Pages
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ADT7310
SPI TIMING SPECIFICATIONS
TA = −55°C to +150°C, VDD = 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns
(10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 2.
Parameter1, 2
t1
t2
t3
t4
t5
t6
t7 4
t8
t9
t10
Limit at TMIN, TMAX (B Version)
0
100
100
30
25
0
60
80
10
80
0
0
60
80
10
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
ns max
ns min
Conditions/Comments
CS falling edge to SCLK active edge setup time3
SCLK high pulse width
SCLK low pulse width
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
SCLK active edge to data valid delay3
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
Bus relinquish time after CS inactive edge
CS rising edge to SCLK edge hold time
CS falling edge to DOUT active time
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
SCLK inactive edge to DOUT high
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 See Figure 2.
3 SCLK active edge is falling edge of SCLK.
4 This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading
capacitances.
CS
SCLK
DIN
DOUT
t1
t2
1
t4
t5
MSB
t9
t3
2
3
7
8
1
2
LSB
t6
MSB
Figure 2. Detailed SPI Timing Diagram
t8
7
8
t10
t7
LSB
ISINK (1.6mA WITH VDD = 5V,
100µA WITH VDD = 3V)
TO
OUTPUT
PIN
10pF
1.6V
ISOURCE (200µA WITH VDD = 5V,
100µA WITH VDD = 3V)
Figure 3. Load Circuit for Timing Characterization
Rev. 0 | Page 4 of 24
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