AD1981BLJSTZ データシートの表示（PDF） - Analog Devices
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AD1981BLJSTZ Datasheet PDF : 32 Pages
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Parameter
Low Level Output Voltage (VOL), IOL = 2 mA
Input Leakage Current
Output Leakage Current
POWER SUPPLY
Power Supply Range (AVDD and DVDD)
Power Dissipation
Analog Supply Current—3.3 V (AVDD)
Digital Supply Current—3.3 V (DVDD)
Power Supply Rejection (100 mV p-p Signal at 1 kHz)1
(At Both Analog and Digital Supply Pins, Both ADCs and DACs)
CLOCK SPECIFICATIONS1
Input Clock Frequency
Recommended Clock Duty Cycle
1 Guaranteed but not tested.
2 Measurements reflect main ADC.
POWER-DOWN STATES
Values presented with VREFOUT not loaded.
Table 3.
Parameter
Fully Active
ADC
DAC
ADC + DAC
Mixer
ADC + Mixer
DAC + Mixer
ADC + DAC + Mixer
Standby
Headphone Standby
Set Bits
No Bits Value
PR0
PR1
PR1, PR0
PR2
PR2, PR0
PR2, PR1
PR2, PR1, PR0
PR5, PR4, PR3, PR2, PR1, PR0
PR6
AD1981BL
Min
Typ Max
Unit
0.1 × DVDD
V
−10
+10
µA
−10
+10
µA
3.0
3.47
V
2.87
mW
39
mA
48
mA
40
dB
24.576
MHz
40
50
60
%
DVDD Typ
AVDD Typ
Unit
47.76
38.9
mA
40.1
34.39
mA
32.8
26.3
mA
13.2
20.55
mA
47.7
19.39
mA
40
14.86
mA
32.77
6.39
mA
13.9
1.15
mA
0
0
mA
47.7
32
mA
TIMING PARAMETERS
Guaranteed over operating temperature range.
Table 4.
Parameter
RESET Active Low Pulse Width
RESET Inactive to BIT_CLK Start-Up Delay
SYNC Active High Pulse Width
SYNC Low Pulse Width
SYNC Inactive to BIT_CLK Start-Up Delay
BIT_CLK Frequency
BIT_CLK Frequency Accuracy
BIT_CLK Period
BIT_CLK Output Jitter1, 2, 3
BIT_CLK High Pulse Width
BIT_CLK Low Pulse Width
SYNC Frequency
Symbol
tRST_LOW
tRST2CLK
tSYNC_HIGH
tSYNC_LOW
tSYNC2CLK
tCLK_PERIOD
tCLK_HIGH
tCLK_LOW
Rev. A | Page 5 of 32
Min
162.8
162.8
32.56
32.56
Typ
1.0
1.3
19.5
12.288
81.4
750
42
38
48.0
Max
±1
2000
48.84
Unit
ms
ns
µs
µs
ns
MHz
ppm
ns
ps
ns
ns
kHz
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