PM7350 データシートの表示（PDF） - PMC-Sierra

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PM7350

DUAL SERIAL LINK PHY MULTIPLEXER

PMC-Sierra 

RELEASED

DATA SHEET

PMC-1980581

Ball

Name

TX8K

RX8K

RCLK

PM7350 S/UNI-DUPLEX

ISSUE 5

DUAL SERIAL LINK PHY MULTIPLEXER

Type

Input

Output

Output

Ball

No. Function

High Speed LVDS Links

B14 The transmit 8 kHz timing reference (TX8K) input

allows a traceable signal to be transmitted to the far

end of the high-speed serial links via TXD1+/- and

TXD2+/-. A rising edge on TX8K is encoded in the

next cell transmitted.

Although TX8K is targeted at a typical need of

transporting an 8 kHz signal, its frequency is not

constrained to 8 kHz. Any frequency less than the

cell rate is permissible.

E13 The receive 8 kHz timing reference (RX8K) output

presents the timing extracted from one of the

receive high-speed serial links, RXD1+/- or

RXD2+/-.

The rising edge of RX8K is accurate to the nearest

byte boundary of the high-speed serial link;

therefore, a small amount of jitter is present. At a

link rate of 155.52 Mb/s, the jitter is 63ns peak-to-

peak.

Pulses on RX8K are always 16 high-speed serial

link bit periods wide (two REFCLK periods).

E11 The Recovered Clock (RCLK) output presents the

byte clock for the active receive high-speed serial

link. The RCLK frequency shall be 0.125 of the

RXD1+/- or RXD2+/- bit rate.

Due to the digital clock recovery technique

employed, jitter is introduced as 12.8 ns phase

steps. If the active link is changed, RCLK can not

be guaranteed to be glitch free. Because of these

two factors, RCLK must be cleaned up by a PLL

before it is suitable for use as a timing reference.

Clocked Data Serial Interface

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

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