PM7350 データシートの表示（PDF） - PMC-Sierra
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PM7350 Datasheet PDF : 241 Pages
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RELEASED
DATA SHEET
PMC-1980581
ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
8 PIN DESCRIPTION
Ball
Name
RXD1+
RXD1-
RXD2+
RXD2-
TXD1+
TXD1-
TXD2+
TXD2-
REFCLK
RES
RESK
ATP0
ATP1
Type
Diff.
LVDS
Input
Diff.
LVDS
Output
Input
Analog
Analog
Ball
No. Function
High Speed LVDS Links
G14 The high-speed receive data (RXD1+/-, RXD2+/-)
G13 inputs present NRZ data from a serial backplane.
J14 Two pairs are provided for redundancy. The active
J13 link may be chosen by the local microprocessor or
determined by a simple handshake.
RXD1+/- and RXD2+/- are truly differential inputs
offering superior common-mode noise rejection.
They have sufficient sensitivity and common-mode
range to support LVDS signals.
H14 The transmit differential data (TXD1+/-, TXD2+/-)
H13 outputs present NRZ encoded data to a serial
K14 backplane. These outputs are open drain current
K13 sinks which interface directly with twisted-pair
cabling or board interconnect. Edge rates are
controlled to minimize radiated emissions.
Both differential links carry identical traffic except
the exact phase relationship is not guaranteed.
P12 The reference clock input (REFCLK) must provide a
jitter-free reference clock. It is used as the
reference clock by both clock recovery and clock
synthesis circuits. Any jitter below 1 MHz is
transferred directly to the TXD1+/- and TXD2+/-
outputs. The high-speed serial interface bit rate is
eight times the REFCLK frequency.
G12 A 4.75kΩ ±1% resistor must be connected between
H11 these two pins to achieve the correct LVDS output
signal levels.
L14 The Analog Test Points (ATP) are provided for
L13 production test purposes. In mission mode they
are high impedance and should be connected to
ground.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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