74123 データシートの表示（PDF） - Fairchild Semiconductor

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74123

Dual Retriggerable Monostable Multivibrator

Fairchild Semiconductor 

RESET OPERATION

These one shots may be reset during the generation of the

output pulse. In the reset mode of operation, an input pulse

on clear sets the reset latch and causes the capacitor to be

fast charged to VCC by turning on transistor Q1 5. When

the voltage on the capacitor reaches VREF2, the reset latch

will clear and then be ready to accept another pulse. If the

clear input is held low, any trigger inputs that occur will be

inhibited and the Q and Q outputs of the output latch will

not change. Since the Q output is reset when an input low-

level is detected on the Clear input, the output pulse T can

be made significantly shorter than the minimum pulse width

specification.

Typical Output Pulse

Width vs. Timing Components

Typical 1ms Pulse Width

Variation vs. Supply

Typical Distribution of Output

Pulse Width, Part to Part

Minimum REXT vs.

Supply Voltage

Typical 1ms Pulse Width

Variation vs. Temperature

Note: R and C are not subjected to temperature. The C is polypropylene.

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