CY7C68034-56LTXI データシートの表示（PDF） - Cypress Semiconductor
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CY7C68034-56LTXI Datasheet PDF : 40 Pages
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CY7C68033/CY7C68034
Table 4. Individual FIFO/GPIF Interrupt Sources
Priority
1
2
3
4
5
6
INT4VEC Value
0x580
0x584
0x588
0x58C
0x590
0x594
Source
EP2PF
EP4PF
EP6PF
EP8PF
EP2EF
EP4EF
7
0x598
EP6EF
8
0x59C
EP8EF
9
0x5A0
EP2FF
10
0x5A4
EP4FF
11
0x5A8
EP6FF
12
0x5AC
EP8FF
13
0x5B0
GPIFDONE
14
0x5B4
GPIFWF
Notes
Endpoint 2 programmable flag
Endpoint 4 programmable flag
Endpoint 6 programmable flag
Endpoint 8 programmable flag
Endpoint 2 empty flag
Endpoint 4 empty flag
Endpoint 6 empty flag
Endpoint 8 empty flag
Endpoint 2 full flag
Endpoint 4 full flag
Endpoint 6 full flag
Endpoint 8 full flag
GPIF operation complete
GPIF waveform
If autovectoring is enabled (AV4EN = 1 in the INTSET-UP
register), the NX2LP-Flex substitutes its INT4VEC byte.
Therefore, if the high byte (‘page’) of a jump-table address is
preloaded at location 0x554, the automatically inserted
INT4VEC byte at 0x555 directs the jump to the correct address
out of the 14 addresses within the page. When the ISR occurs,
the NX2LP-Flex pushes the program counter to its stack and
then jumps to address 0x553; it expects to find a ‘jump’
instruction to the ISR Interrupt service routine here.
Reset and Wakeup
Reset Pin
The input pin RESET#, resets the NX2LP-Flex when asserted.
This pin has hysteresis and is active LOW. When a crystal is
used as the clock source for the NX2LP-Flex, the reset period
must enable the stabilization of the crystal and the PLL. This
reset period should be approximately 5 ms after VCC has
reached 3.0V. If the crystal input pin is driven by a clock signal,
the
3.0
internal PLL
V[1]. Figure 5
stabilizes in 200 s after VCC
shows a POR condition and a
has reached
reset applied
during operation. A POR is defined as the time reset is asserted
while power is being applied to the circuit. A powered reset is
defined to be when the NX2LP-Flex has previously been
powered on and operating and the RESET# pin is asserted.
For more information on power on reset implementation for the
EZ-USB family of products, refer to the application note
EZ-USB FX2™/AT2™/SX2™.
Figure 5. Reset Timing Plots
RESET#
VCC
TRESET
Power-on Reset
VIL
3.3 V
3.0 V
0V
RESET#
VCC
VIL
3.3 V
0V
TRESET
Powered Reset
Note
1. If the external clock is powered at the same time as the CY7C68033/CY7C68034 and has a stabilization wait period, it must be added to the 200 s.
Document Number: 001-04247 Rev. *J
Page 9 of 40
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