HEF4518B データシートの表示（PDF） - NXP Semiconductors.
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HEF4518B Datasheet PDF : 14 Pages
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HEF4518B
Dual BCD counter
Rev. 8 — 19 April 2016
Product data sheet
1. General description
The HEF4518B is a dual 4-bit internally synchronous BCD counter. The counter has an
active HIGH clock input (nCP0) and an active LOW clock input (nCP1), buffered outputs
from all four bit positions (nQ0 to nQ3) and an active HIGH overriding asynchronous
master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of
the nCP0 input if nCP1 is HIGH or the HIGH-to-LOW transition of the nCP1 input if nCP0
is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter and the other
clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0
to nQ3 = LOW) independent of nCP0, nCP1. Schmitt trigger action in the clock input
makes the circuit highly tolerant of slower clock rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
Multistage synchronous counting
Multistage asynchronous counting
Frequency dividers
4. Ordering information
Table 1. Ordering information
All types operate from 40 C to +85 C
Type number
Package
Name
Description
HEF4518BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT109-1
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