XRT83SH38 データシートの表示（PDF） - Exar Corporation

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XRT83SH38

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

Exar Corporation 

REV. 1.0.7

XRT83SH38

8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

SIGNAL NAME

µPCLK/ATAOS

INT

BGA

LEAD

#

TYPE

DESCRIPTION

T13 I Synchronous Microprocessor Clock/Automatic Transmit All Ones

Host Mode

This synchronous input clock is used as the internal master clock to the microproces-

sor interface when configured for in a synchronous mode.

Hardware Mode

This pin is used select an all ones signal to the line interface through TTIP/TRING any

time that a loss of signal occurs. This feature is avaiable in Host mode by program-

ming the appropriate global register.

NOTE: Internally pulled “Low” with a 50kΩ resistor.

L16 O Interrupt Output/Turns Ratio Select (External Impedance Mode)

Host Mode

This signal is asserted "Low" when a change in alarm status occurs. Once the status

registers have been read, the interrupt pin will return "High". GIE (Global Interrupt

Enable) must be set "High" in the appropriate global register to enable interrupt gen-

eration.

NOTES:

1. This pin is an open-drain output that requires an external 10KΩ pull-up

resistor.

2. Internally pulled “Low” with a 50kΩ resistor.

JITTER ATTENUATOR

SIGNAL

NAME

JASEL0

JASEL1

BGA

LEAD #

A14

B13

TYPE

DESCRIPTION

I Jitter Attenuator Select Pins Hardware Mode

JASEL[1:0] pins are used to place the jitter attenuator in the transmit path, the receive

path or to disable it.

JASEL1 JASEL0 JA Path

0

0

Disabled

0

1

Transmit

1

0

Receive

1

1

Receive

JA BW Hz

T1

E1

----- -----

3

10

3

10

3

1.5

FIFO Size

--------

32/32

32/32

64/64

NOTE: These pins are internally pulled “Low” with 50kΩ resistors.

CLOCK SYNTHESIZER

SIGNAL NAME

BGA

LEAD #

MCLKOUT

H1

TYPE

DESCRIPTION

O Synthesized Master Clock Output

This signal is the output of the Master Clock Synthesizer PLL which is at T1 or E1

rate based upon the mode of operation.

12

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