XRT83SL34IV データシートの表示（PDF） - Exar Corporation

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XRT83SL34IV

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

Exar Corporation 

XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.0.8

PRELIMINARY

FIGURE 2. BLOCK DIAGRAM OF THE XRT83SL34 T1/E1/J1 LIU (HARDWARE MODE)

MCLKE1

MCLKT1

C LK S E L[2:0]

TPOS_n/TDATA_n

T N E G _n/C O D E S _n

TCLK_n

RCLK_n

R N E G _n/LC V _n

RPOS_n/RDATA_n

RLOS_n

HW /HOST

GAUGE

JASEL1

JASEL0

RXTSEL

TXTSEL

TERSELR

XRES0

RXRES1

MASTER CLOCK SYNTHESIZER

One of four Channels, CHANNEL_n - (n=0 : 3)

QRSS

PAT T ERN

GENE RAT OR

HDB3/

B8ZS

ENCODER

TX/RX JITT ER

ATTENUATOR

T IM IN G

CONTROL

DFM

D R IV E

M O N IT O R

TX FILTER

& PULSE

SHAPER

L IN E

D R IV E R

QRSS ENABLE

QRSS

DETECTOR

NETWORK

LOOP

DETECTOR

REMOTE

LOOPBACK

D IG IT A L

LOOPBACK

LOOPBACK

ENABLE

HDB3/

B8ZS

DECODER

TX/RX JITT ER

ATTENUATOR

TIMING &

DATA

RECOVERY

L B O [3 :0]

PEAK

DETECTOR

& SLICER

NLCD ENABLE

LOS

DETECTOR

AIS

DETECTOR

E Q U A L IZ E R

CONTROL

LOCAL

ANALOG

LOOPBACK

RX

E Q U A L IZ E R

TEST

HARWARE CONTROL

MCLKOUT

TAOS_n

DMO_n

T T IP _n

TRING_n

TXON_n

RTIP_n

RRING_n

LOOP1_n

LOOP0_n

ICT

RESET

T R A T IO

SR/DR

E Q C [4:0]

TCLKE

RCLKE

RXMUTE

ATAOS

FEATURES

• Fully integrated eight channel short-haul transceiv-

ers for E1,T1 or J1 applications

• Programable Transmit Pulse Shaper for E1,T1 or J1

short-haul interfaces

• Five fixed transmit pulse settings for T1 short-haul

applications plus a fully programmable waveform

generator for transmit output pulse shaping for both

T1 and E1 modes.

• Selectable receiver sensitivity from 0 to 36dB cable

loss

• Receive monitor mode handles 0 to 29dB resistive

attenuation along with 0 to 6dB of cable attenuation

for E1 and 0 to 3dB of cable attenuation for T1

modes

• Supports 75Ω and 120Ω (E1), 100Ω (T1) and 110Ω

(J1) applications

• Internal and/or external impedance matching for

75Ω, 100Ω, 110Ω and 120Ω

• Tri-State transmit output and receive input capabil-

ity for redundancy applications

• Provides High Impedance for Tx and Rx during

power off

• Transmit return loss meets or exceeds ETSI 300-

166 standard

• On-chip digital clock recovery circuit for high input

jitter tolerance

• Crystal-less digital jitter attenuator with 32-bit or 64-

bit FIFO selectable either in transmit or receive path

• On-chip frequency multiplier generates T1 or E1

Master clocks from variety of external clock sources

• High receiver interference immunity

• On-chip transmit short-circuit protection and limit-

ing, and driver fail monitor output (DMO)

• Receive loss of signal (RLOS) output

• On-chip HDB3/B8ZS/AMI encoder/decoder func-

tions

• QRSS pattern generator and detection for testing

and monitoring

• Error and Bipolar Violation Insertion and Detection

• Receiver Line Attenuation Indication Output in 1dB

steps

• Network Loop-Code Detection for automatic Loop-

Back Activation/Deactivation

• Transmit All Ones (TAOS) and In-Band Network

Loop Up and Down code generators

• Supports Local Analog, Remote, Digital and Dual

Loop-Back Modes

• Meets or exceeds T1 and E1 short-haul network

access specifications in ITU G.703, G.775, G.736

2

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