XRT83SL30(2003) データシートの表示（PDF） - Exar Corporation

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XRT83SL30
(Rev.:2003)

SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

Exar Corporation 

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XRT83SL30

SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.0.4

TRANSMITTER

SIGNAL NAME

TTIP

TRING

TPOS

TDATA

TNEG

CODES

TCLK

TCLKE

TXON

PIN #

8

10

61

62

60

57

58

TYPE

O

O

I

DESCRIPTION

Transmitter Tip Output

Positive differential transmit output to the line.

Transmitter Ring Output

Negative differential transmit output to the line.

Transmitter Positive Data Input

In dual-rail mode, this signal is the positive-rail input data for the transmitter.

Transmitter Data Input

In single-rail mode, this pin is used as the NRZ input data for the transmitter.

NOTE: Internally pulled “Low” with a 50kΩ resistor.

I

Transmitter Negative NRZ Data Input

In dual-rail mode, this signal is the negative-rail input data for the transmitter.

In single-rail mode, this pin can be left unconnected.

Coding Select

In Hardware Mode and with single-rail mode selected, connecting this pin

"Low" enables HDB3 in E1 or B8ZS in T1 encoding and decoding. Connect-

ing this pin "High" selects AMI data format.

NOTE: Internally pulled “Low” with a 50kΩ resistor.

I

Transmitter Clock Input

E1 rate at 2.048MHz ± 50ppm

T1 rate at 1.544MHz ± 32ppm

During normal operation, both in Host Mode and Hardware Mode, TCLK is

used for sampling input data at TPOS/TDATA and TNEG/CODES while

MCLK is used as the timing reference for the transmit pulse shaping circuit.

I

Transmit Clock Edge

In Hardware Mode, with this pin set to a "High", transmit input data is sam-

pled at the rising edge of TCLK. With this pin tied "Low", input data are sam-

pled at the falling edge of TCLK.

NOTE: Internally pulled “Low” with a 50kΩ resistor.

I

Transmitter Turn On

In Hardware Mode, setting this pin "High" turns on the Transmit Section. In

this mode, when TXON = “0”, TTIP and TRING driver outputs will be tri-

stated.

In Host Mode, setting bit 5 (TXONCTL) to “1”, in Register 18 (12h), control of

the transmitter output is transferred to the hardware pin TXON.

NOTE: Internally pulled "Low" with a 50kΩ resistor.

6

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