XRT83SL30(2003) データシートの表示（PDF） - Exar Corporation

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XRT83SL30
(Rev.:2003)

SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

Exar Corporation 

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XRT83SL30

SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.0.4

Internal Receive Termination Mode ................................................................................................................. 26

TABLE 6: RECEIVE TERMINATION CONTROL ................................................................................................ 26

Figure 11. Simplified Diagram for the Internal Receive and Transmit Termination Mode .............. 26

TABLE 7: RECEIVE TERMINATIONS ............................................................................................................. 27

Figure 12. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) ................... 27

TRANSMITTER ........................................................................................................................................ 28

Transmit Termination Mode ............................................................................................................................. 28

External Transmit Termination Mode ............................................................................................................... 28

Figure 13. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) ......................... 28

TABLE 8: TRANSMIT TERMINATION CONTROL ............................................................................................. 28

TABLE 9: TERMINATION SELECT CONTROL ................................................................................................. 28

REDUNDANCY APPLICATIONS ............................................................................................................. 29

TABLE 10: TRANSMIT TERMINATION CONTROL ........................................................................................... 29

TABLE 11: TRANSMIT TERMINATIONS ......................................................................................................... 29

TYPICAL REDUNDANCY SCHEMES ..................................................................................................... 30

Figure 14. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy ............. 31

Figure 15. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy .................... 31

Figure 16. Simplified Block Diagram - Transmit Section for N+1 Redundancy ............................... 32

Figure 17. Simplified Block Diagram - Receive Section for N+1 Redundancy ................................. 33

PATTERN TRANSMIT AND DETECT FUNCTION ............................................................................................... 34

TRANSMIT ALL ONES (TAOS) .................................................................................................................... 34

NETWORK LOOP CODE DETECTION AND TRANSMISSION .............................................................................. 34

TABLE 12: PATTERN TRANSMISSION CONTROL ............................................................................................ 34

TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS) ......................................................... 35

TABLE 13: LOOP-CODE DETECTION CONTROL ........................................................................................... 35

LOOP-BACK MODES ................................................................................................................................... 37

LOCAL ANALOG LOOP-BACK (ALOOP) ....................................................................................................... 37

TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE .............................................................................. 37

TABLE 15: LOOP-BACK CONTROL IN HOST MODE ........................................................................................ 37

Figure 18. Local Analog Loop-back signal flow .................................................................................. 37

REMOTE LOOP-BACK (RLOOP) ................................................................................................................. 38

Figure 19. Remote Loop-back mode with jitter attenuator selected in receive path ....................... 38

Figure 20. Remote Loop-back mode with jitter attenuator selected in Transmit path .................... 38

DIGITAL LOOP-BACK (DLOOP) .................................................................................................................. 39

DUAL LOOP-BACK ...................................................................................................................................... 39

Figure 21. Digital Loop-back mode with jitter attenuator selected in Transmit path ...................... 39

Figure 22. Signal flow in Dual loop-back mode ................................................................................... 39

HOST MODE SERIAL INTERFACE OPERATION ........................................................... 40

USING THE MICROPROCESSOR SERIAL INTERFACE ...................................................................................... 40

Figure 23. Microprocessor Serial Interface Data Structure ................................................................ 41

TABLE 16: MICROPROCESSOR REGISTER ADDRESS ................................................................................... 42

TABLE 17: MICROPROCESSOR REGISTER BIT MAP ..................................................................................... 42

TABLE 18: MICROPROCESSOR REGISTER #0 BIT DESCRIPTION .................................................................... 44

TABLE 19: MICROPROCESSOR REGISTER #1 BIT DESCRIPTION .................................................................... 44

TABLE 20: MICROPROCESSOR REGISTER #2 BIT DESCRIPTION .................................................................... 47

TABLE 21: MICROPROCESSOR REGISTER #3 BIT DESCRIPTION .................................................................... 49

TABLE 22: MICROPROCESSOR REGISTER #4 BIT DESCRIPTION .................................................................... 51

TABLE 23: MICROPROCESSOR REGISTER #5 BIT DESCRIPTION .................................................................... 52

TABLE 24: MICROPROCESSOR REGISTER #6 BIT DESCRIPTION .................................................................... 54

TABLE 25: MICROPROCESSOR REGISTER #7 BIT DESCRIPTION .................................................................... 55

TABLE 26: MICROPROCESSOR REGISTER #8 BIT DESCRIPTION .................................................................... 55

TABLE 27: MICROPROCESSOR REGISTER #9 BIT DESCRIPTION .................................................................... 56

TABLE 28: MICROPROCESSOR REGISTER #10 BIT DESCRIPTION .................................................................. 56

TABLE 29: MICROPROCESSOR REGISTER #11 BIT DESCRIPTION .................................................................. 56

TABLE 30: MICROPROCESSOR REGISTER #12 BIT DESCRIPTION .................................................................. 57

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