XRT83SL30(2003) データシートの表示（PDF） - Exar Corporation
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XRT83SL30
(Rev.:2003)
(Rev.:2003)
Exar Corporation
XRT83SL30 Datasheet PDF : 76 Pages
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XRT83SL30
áç
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.4
PRELIMINARY
FIGURE 2. BLOCK DIAGRAM OF THE XRT83SL30 T1/E1/J1 LIU (HARDWARE MODE)
MCLKE1
MCLKT1
CLKSEL[2:0]
TXTEST[0:2]
INSBPV
TPOS / TDATA
TNEG / CODES
TCLK
QRPD
RCLK
RNEG / LCV
RPOS / RDATA
NLCD
RLOS
HW/HOST
GAUGE
JASEL1
JASEL0
RXTSEL
TXTSEL
TERSEL1
TERSEL0
RXRES1
RXRES0
MASTER CLOCK SYNTHESIZER
QRSS
PATTERN
GENERATOR
QRSS ENABLE
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TAOS
ENABLE
TIMING
CONTROL
DFM
DRIVE
MONITOR
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
LOOPBACK
ENABLE
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
LBO[3:0]
PEAK
DETECTOR
& SLICER
LOCAL
ANALOG
LOOPBACK
RX
EQUALIZER
NLCD ENABLE
LOS
DETECTOR
AIS
DETECTOR
EQUALIZER
CONTROL
TEST
HARWARE CONTROL
MCLKOUT
DMO
TTIP
TRING
TXON
RTIP
RRING
LOOP1
LOOP0
AISD
ICT
JABW
TRATIO
SR/DR
EQC[4:0]
TCLKE
RCLKE
RXMUTE
ATAOS
RESET
FEATURES
• Fully integrated single-channel short-haul trans-
ceiver for E1,T1 or J1 applications
• Programmable Transmit Pulse Shaper for E1,T1 or
J1 short-haul interfaces
• Five fixed transmit pulse settings for T1 short-haul
applications plus a fully programmable waveform
generator for transmit output pulse shaping
• High receiver interference immunity
• Receive monitor mode handles 0 to 29dB resistive
attenuation along with 0 to 6dB of cable attenuation
for both T1 and E1 modes
• Supports 75Ω and 120Ω (E1), 100Ω (T1) and 110Ω
(J1) applications.
• Internal and/or external impedance matching for
75Ω,100Ω, 110Ω and 120Ω.
• Tri-State transmit output and receive input capabil-
ity for redundancy applications
• Provides High Impedance for Tx and Rx during
power off
• Transmit return loss meets or exceeds ETSI 300
166 standard
• On-chip digital clock recovery circuit for high input
jitter tolerance
• Crystal-less digital jitter attenuator with 32-bit or 64-
bit FIFO Selectable either in transmit or receive
path
• On-chip frequency multiplier generates T1 or E1
Master clocks from variety of external clock sources
• On-chip transmit short-circuit protection and limit-
ing, and driver fail monitor output (DMO)
• Receive loss of signal (RLOS) output
• On-chip HDB3/B8ZS/AMI encoder/decoder
• QRSS pattern generation and detection for testing
and monitoring
• Error and Bipolar Violation Insertion and Detection
• Receiver Line Attenuation Indication Output in 1dB
steps
• Network Loop-Code Detection for automatic Loop-
Back Activation/Deactivation
• Transmit All Ones (TAOS) and In-Band Network
Loop Up and Down code generators
• Supports Local Analog, Remote, Digital and Dual
Loop-Back Modes
• Meets or exceeds T1 and E1 short-haul network
access specifications in ITU G.703, G.775, G.736
and G.823; TR-TSY-000499; ANSI T1.403 and
T1.408; ETSI 300-166 and AT&T Pub 62411
• Supports both Hardware and serial Microprocessor
interface for programming
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