XRT83SL28(2003) データシートの表示（PDF） - Exar Corporation
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XRT83SL28 Datasheet PDF : 47 Pages
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PRELIMINARY
RECEIVER SECTION
NAME
PIN
RTIP7
75
RTIP6
87
RTIP5
94
RTIP4
106
RTIP3
34
RTIP2
22
RTIP1
15
RTIP0
3
RRING7
76
RRING6
86
RRING5
95
RRING4
105
RRING3
33
RRING2
23
RRING1
14
RRING0
4
XRT83SL28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
REV. P1.0.1
TYPE
I
DESCRIPTION
Receive Differential Tip Input
RTIP is the positive differential input from the line interface. Along with the
RRING signal, these pins should be coupled to a 1:1 transformer for proper
operation.
I
Receive Differential Ring Input
RRING is the negative differential input from the line interface. Along with the
RTIP signal, these pins should be coupled to a 1:1 transformer for proper oper-
ation.
TRANSMITTER SECTION
NAME
PIN
TxOE
9
TYPE
I
DMO7
73
O
DMO6
72
DMO5
109
DMO4
108
DMO3
36
DMO2
37
DMO1
144
DMO0
1
TCLK7
69
I
TCLK6
66
TCLK5
115
TCLK4
112
TCLK3
40
TCLK2
43
TCLK1
138
TCLK0
141
DESCRIPTION
Transmit Output Enable
Upon power up, the transmitters are tri-stated. Enabling the transmitters is
selected through the serial microprocessor interface by programming the
appropriate channel register if this pin is pulled "High". If the TxOE pin is
pulled "Low", all 8 transmitters are tri-stated.
NOTE: TxOE is ideal for redundancy applications. See the Redundancy
Applications Section of this datasheet for more details. Internally
pulled "Low" with a 50KΩ resistor.
Digital Monitor Output
When no transmit output pulse is detected for more than 128 TCLK cycles, the
DMO pin will go "High" for a minimum of one TCLK cycle. DMO will remain
"High" until the transmitter sends a valid pulse.
Transmit Clock Input
TCLK is the input facility clock used to sample the incoming TPOS/TNEG data.
TPOS/TNEG data can be sampled on either edge of TCLK selected by TCLK-
inv in the appropriate global register.
NOTE: TCLKinv is a global setting that applies to all 8 channels.
7
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