XRT83SL28IB(2003) データシートの表示（PDF） - Exar Corporation

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XRT83SL28IB
(Rev.:2003)

8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT

Exar Corporation 

PRELIMINARY

XRT83SL28

8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT

REV. P1.0.1

TABLE OF CONTENTS

FIGURE 1. HOST MODE BLOCK DIAGRAM OF THE XRT83SL28................................................................................................................ 1

FIGURE 2. HARDWARE MODE BLOCK DIAGRAM OF THE XRT83SL28 ....................................................................................................... 2

FIGURE 3. PIN OUT OF THE XRT83SL28................................................................................................................................................ 4

1.0 RECEIVE PATH LINE INTERFACE .................................................................................................... 14

FIGURE 4. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH LINE TERMINATION (RTIP/RRING) ....................................................... 14

1.1 INTERNAL TERMINATION ............................................................................................................................ 14

FIGURE 5. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .......................................................................................... 14

TABLE 1: SELECTING THE INTERNAL IMPEDANCE ................................................................................................................................... 14

1.2 PEAD DETECTOR .......................................................................................................................................... 15

1.3 CLOCK AND DATA RECOVERY ................................................................................................................... 15

FIGURE 6. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK..................................................................................................... 15

FIGURE 7. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK................................................................................................... 15

1.4 RECEIVE SENSITIVITY .................................................................................................................................. 16

FIGURE 8. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY .............................................................................................. 16

1.5 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ............................................................ 16

TABLE 2: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG ................................................................................................................ 16

1.5.1 RLOS (RECEIVER LOSS OF SIGNAL)...................................................................................................................... 17

1.5.2 AIS (ALARM INDICATION SIGNAL) .......................................................................................................................... 17

1.5.3 LCV (LINE CODE VIOLATION DETECTION) ............................................................................................................ 17

1.6 RECEIVE JITTER ATTENUATOR .................................................................................................................. 17

1.7 HDB3 DECODER ............................................................................................................................................ 18

1.8 ARAOS (AUTOMATIC RECEIVE ALL ONES) ............................................................................................... 18

FIGURE 9. IMPLIFIED BLOCK DIAGRAM OF THE ARAOS FUNCTIONRPOS/RNEG/RCLK ......................................................................... 18

1.9 RPOS/RNEG/RCLK ........................................................................................................................................ 18

FIGURE 10. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ......................................................................................... 18

FIGURE 11. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ............................................................................................ 19

2.0 TRANSMIT PATH LINE INTERFACE ................................................................................................. 20

FIGURE 12. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH ......................................................................................................... 20

2.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 20

FIGURE 13. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK...................................................................................................... 20

FIGURE 14. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK........................................................................................................ 20

2.2 HDB3 ENCODER ............................................................................................................................................ 21

2.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................... 21

TABLE 3: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG.................................................................................................................. 21

TABLE 4: EXAMPLES OF HDB3 ENCODING ............................................................................................................................................ 21

TABLE 5: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS........................................................................................... 21

2.4 TAOS (TRANSMIT ALL ONES) ..................................................................................................................... 22

FIGURE 15. TAOS (TRANSMIT ALL ONES)ATAOS (AUTOMATIC TRANSMIT ALL ONES)........................................................................... 22

2.5 ATAOS (AUTOMATIC TRANSMIT ALL ONES) ............................................................................................ 22

FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION ..................................................................................................... 22

2.6 TRANSMIT PULSE SHAPER AND FILTER ................................................................................................... 22

2.7 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 22

2.8 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 22

FIGURE 17. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ......................................................................................... 23

3.0 E1 APPLICATIONS ............................................................................................................................. 24

3.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 24

3.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 24

FIGURE 18. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK................................................................................................ 24

3.1.2 REMOTE LOOPBACK ................................................................................................................................................ 24

FIGURE 19. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK .......................................................................................................... 24

3.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 25

FIGURE 20. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK ........................................................................................................... 25

3.2 LINE CARD REDUNDANCY .......................................................................................................................... 26

3.2.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 26

3.2.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 26

FIGURE 21. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ................................................ 26

3.2.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 27

FIGURE 22. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY.................................................. 27

3.2.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 27

3.2.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 28

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