SAA7500 データシートの表示（PDF） - Philips Electronics

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SAA7500

Digital satellite radio broadcasting tuner decoder (SAT-2)

Philips Electronics 

Philips Semiconductors

Digital satellite radio broadcasting tuner

decoder (SAT-2)

Product specification

SAA7500

Demultiplexer

After synchronization, the beginning of a frame is marked and the digital signals are defined as to their assignment.

First the non-scrambled special service bit from the half frame A is taken out. The rest of both half frames are

unscrambled and demultiplexed so that each half frame is split into two substreams with a rate of 5.12 Mbit/s (see

Technische Richtlinie ARD/ZDF Nr. 3R1, main frame specification). Using the inputs from the synchronization circuit and

the programme selector (inputs PA, PB, PC and PD) the demultiplexer locks on to the selected programme block and

generates all the control signals required for further signal processing.

Error correction

The error correction circuit provides for exact identification of two errors in a 63/44 BCH block and correction of the

incorrect bits. In the event of more than two errors the identification circuit can identify incorrect BCH blocks with up to

five errors.

The BCH block is operated on by a syndrome calculator, the results controls the lines of an error correction matrix.

The output of this matrix corrects (inverts) the incorrect bits when data is shifted out from its buffer. The BCH block is

then fed through a second syndrome calculator. In the event of more than two errors the result of the whole calculation

will be other than zero. This information provides the concealment in the next stages.

The two adjacent samples related to the detected incorrect sample are added and divided by two, the result replaces the

incorrect sample (interpolation). In the event of successive bad samples the last corrected sample is held until a good

sample is detected (hold function). A high error frequency in the event of synchronization loss will activate the muting

function and set the output data to zero.

This information, if concealment is not active, is used in the synchronization circuit as described in that section.

When the samples are correct it can be assumed that the synchronization is also correct.

Scale factor, programme type evaluation and shift sunction

The transmitted samples are returned to their original range of values by the scale factor, which is obtained by decoding

the ZI-subframe. The start of this frame is coupled to the start of the special services frame, synchronization for this frame

uses the same principle as for the main frame. In the scale factor evaluation unit the BCH 14/6 code words (three times

transmitted) are fed into a majority selection circuit working at bit level. Subsequently the error check and the correction

of a maximum of two errors is carried out.

The SAA7500 contains the synchronization word detection and error check for the subframe synchronization word with

its repetition time of 2 ms. The programme type evaluation with its superior synchronization has to be performed external

to the chip, for example, by a microcomputer. For this purpose data is available in 8-bit blocks at a serial interface (INTR,

PAUP and TUP; block rate = 4000/s). The same microcomputer can also perform the programme selection (inputs PA,

PB, PC and PD).

At the input to the concealment buffer the corrected 11 bits (MSB) are combined with the 3 unprotected transmitted bits

(LSB). The scale factor determines the required shift-back operations needed to convert the transmitted values back into

the original values. Voids that occur are filled with noughts or ones corresponding to the sign bit. The shift-back and filling

of voids ensures that no incorrect bits occur above the range defined by the scale factor. The upper 16 bits represent the

regenerated audio sample.

September 1989

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