W48S87(1999) データシートの表示（PDF） - Cypress Semiconductor

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W48S87
(Rev.:1999)

Spread Spectrum 3 DIMM Desktop Clock

Cypress Semiconductor 

PRELIMINARY

W48S87-04

3.3V AC Electrical Characteristics (CPU3.3#_2.5 Input = 0) (continued)

48-/24-MHZ Clock Outputs (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

f

Frequency, Actual

Determined by PLL divider ratio

(see n/m below)

fD

Deviation from 48 MHz (48.008 – 48)/48

m/n

PLL Ratio

(14.31818 MHz x 57/17 = 48.008 MHz)

tR

Output Rise Edge Rate Measured from 0.4V to 2.4V

tF

Output Fall Edge Rate Measured from 2.4V to 0.4V

tD

Duty Cycle

Measured on rising and falling edge at 1.5V

tJC

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.5V. Maximum

difference of cycle time between two adjacent

cycles.

fST

Frequency Stabilization Assumes full supply voltage reached within

from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to

frequency stabilization.

Zo

AC Output Impedance Average value during switching transition.

Used for determining series termination value.

CPU = 60/66.8 MHz

Min. Typ. Max.

48.008/24.004

+167

57/17

1

4

1

4

40

55

500

3

15

20

30

Unit

MHz

ppm

V/ns

V/ns

%

ps

ms

Ω

Serial Input Port

Parameter

Description

fSCLOCK

tSTHD

tLOW

tHIGH

tDSU

tDHD

SCLOCK Frequency

Start Hold Time

SCLOCK Low Time

SCLOCK High Time

Data Setup Time

Data Hold Time

tR

tF

tSTSU

tSPF

tSP

Rise Time, SDATA and

SCLOCK

Fall Time, SDATA and

SCLOCK

Stop Setup Time

Bus Free Time between

Stop and Start Condition

Allowable Noise Spike

Pulse Width

Test Condition

Normal Mode

(Transmitter should provide a 300-ns hold

time to ensure proper timing at the receiver.)

From 0.3VDD to 0.7VDD

Min.

0

4.0

4.7

4.0

250

0

From 0.7VDD to 0.3VDD

4.0

4.7

Typ.

Max.

100

1000

300

50

Unit

kHz

µs

µs

µs

ns

ns

ns

ns

µs

µs

ns

19

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